Patents by Inventor Eung Jung Kim

Eung Jung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112629
    Abstract: An example apparatus includes: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; first driver circuitry having a terminal coupled to the control terminal of the first transistor; second driver circuitry having a terminal coupled to the control terminal of the second transistor; and gate balancing circuitry having a first terminal and a second terminal, the first terminal of the gate balancing circuitry coupled to the control terminal of the first transistor and the terminal of the first driver circuitry, the second terminal of the gate balancing circuitry coupled to the control terminal of the second transistor.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Eung Jung Kim, Xiaochun Zhao, Abidur Rahman, Sualp Aras
  • Patent number: 12237662
    Abstract: In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: February 25, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Wenchao Qu
  • Publication number: 20250048721
    Abstract: Described examples include an integrated circuit having first and second transistors. The first transistor includes a plurality of trenches extending into a semiconductor substrate and a plurality of source regions, each source region located between a pair of adjacent trenches. A first source terminal is connected to the plurality of source regions. The second transistor includes a central source region between a pair of the trenches and a second source terminal connected to the central source region. The second source terminal is conductively isolated from the first source terminal.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Eung Jung Kim, Thomas Grebs, Sunglyong Kim, Sungho Beck, Wei Fu, Xiaochun Zhao, Arjun Pankaj
  • Publication number: 20240259010
    Abstract: A transistor is coupled between a first voltage input and a voltage output in a first current path. First circuitry is coupled to a second voltage input, a control terminal of the transistor, and the voltage output. Second circuitry is coupled between the control terminal and ground in a second current path and between the control terminal and ground in a third current path parallel to the second current path. The second current path includes the control terminal, first and second terminals of the second circuitry, and ground. The third current path includes the control terminal, a second and the third terminal of the second circuitry, and ground. Third circuitry is coupled between the control terminal and the voltage output in a fourth current path. The fourth current path includes the control terminal, first and second terminals of the third circuitry, and the voltage output.
    Type: Application
    Filed: August 25, 2023
    Publication date: August 1, 2024
    Inventors: Xiaochun Zhao, Abidur Rahman, Eung Jung Kim, Tianhong Yang, Huijuan Li
  • Publication number: 20240006869
    Abstract: In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 4, 2024
    Inventors: Eung Jung KIM, Wenchao QU
  • Patent number: 11799281
    Abstract: In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Wenchao Qu
  • Patent number: 11781920
    Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: October 10, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Abidur Rahman
  • Publication number: 20230236247
    Abstract: In an example, a system includes a first power stage including a first power field effect transistor (FET) and a first sense transistor coupled to the first power FET. The system also includes a second power stage including a second power FET and a second sense transistor coupled to the second power FET, where the second power stage is smaller than the first power stage. The system includes a first switch coupled to a gate and a drain of the first power FET and a second switch coupled to the first power stage and the second power stage. The system also includes a sense amplifier coupled to the second switch, where the first power stage, the second power stage, and the sense amplifier are coupled to a load terminal.
    Type: Application
    Filed: October 27, 2022
    Publication date: July 27, 2023
    Inventors: MD Abidur RAHMAN, Eung Jung KIM, Wenchao QU
  • Patent number: 11574902
    Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Kyle Clifton Schulmeyer, Sualp Aras, Md Abidur Rahman, Xiaochun Zhao
  • Publication number: 20220360068
    Abstract: In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.
    Type: Application
    Filed: October 29, 2021
    Publication date: November 10, 2022
    Inventors: Eung Jung KIM, Wenchao QU
  • Publication number: 20220214226
    Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Eung Jung Kim, Abidur Rahman
  • Patent number: 11320320
    Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Abidur Rahman
  • Patent number: 11184000
    Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Sualp Aras, Abidur Rahman
  • Publication number: 20200251465
    Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: EUNG JUNG KIM, KYLE CLIFTON SCHULMEYER, SUALP ARAS, MD ABIDUR RAHMAN, XIAOCHUN ZHAO
  • Patent number: 10554203
    Abstract: In some examples, the disclosure includes a circuit including a power field effect transistor (FET), a gate pull-down circuit, a pull-down bias circuit, and a radio frequency (RF) detector coupled to the source terminal of the power FET and the pull-down bias circuit. In an example, the RF detector circuit is configured to detect a presence of an alternating current signal at a source terminal of the power FET when the power FET is in a non-conductive state and control the pull-down bias circuit to bias the gate pull-down circuit to create a low impedance path between a gate terminal of the power FET and the source terminal of the power FET when the power FET is in the non-conductive state and the alternating current signal is present at the source terminal of the power FET.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 4, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sualp Aras, Eung Jung Kim, Abidur Md Rahman
  • Publication number: 20200033198
    Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
    Type: Application
    Filed: April 26, 2019
    Publication date: January 30, 2020
    Inventors: Eung Jung Kim, Abidur Rahman
  • Patent number: 10422818
    Abstract: An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: September 24, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Tikno Harjono, Vijay Krishnamurthy, Min Chu, Kuntal Joardar, Gary Eugene Daum, Subrato Roy, Vinayak Hegde, Ankur Chauhan, Sathish Vallamkonda, Md Abidur Rahman, Eung Jung Kim
  • Publication number: 20190214980
    Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.
    Type: Application
    Filed: June 6, 2018
    Publication date: July 11, 2019
    Inventors: Eung Jung Kim, Sualp Aras, Abidur Rahman
  • Publication number: 20190204361
    Abstract: An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Tikno HARJONO, Vijay KRISHNAMURTHY, Min CHU, Kuntal JOARDAR, Gary Eugene DAUM, Subrato ROY, Vinayak HEGDE, Ankur CHAUHAN, Sathish VALLAMKONDA, Md Abidur RAHMAN, Eung Jung KIM
  • Patent number: 9942956
    Abstract: Embodiments of the invention improve efficiency and address the stability issues that arise when a boost converter is used for both backlight WLEDs and camera flash applications, which require increased voltage or output voltage less than input voltage. In prior solutions, boost converters may suffer poor efficiency when operating in a fixed high output voltage mode or may lose stability by not properly regulating their output when operating in a step-down voltage mode. To improve efficiency of the boost converter, the present invention uses a 100%-pass mode topology when the battery voltage is high enough to support the diode voltage required for the backlight WLEDs or the camera flash. On the other hand, when the battery voltage drops below the required voltage, then the converter switches automatically to boost mode to generate a sufficient output voltage to drive the diodes to the required current level.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 10, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Wenliang Chen, Eung Jung Kim