Abstract: In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the fuse barrier pattern.

Abstract: In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the fuse barrier pattern.

Abstract: A cell array of a NAND type ferro-dielectric memory is disclosed. The cell array of ferro-dielectric memory system, including: a plurality of unit cell strings coupled to one bit line; and a plurality of string selectors between each of the unit cell strings and the bit line, wherein only one unit cell string is connected to the bit line through one string selectors. The present invention can decrease a size of cell by eliminating a bit line contact formed in cells and controls a bit line capacitance by using selection transistor, therefore, the present invention can control optimum bit line capacitance by gaining the maximum sense margin.

Abstract: A cell array of a NAND type ferro-dielectric memory is disclosed. The cell array of ferro-dielectric memory system, including: a plurality of unit cell strings coupled to one bit line; and a plurality of string selectors between each of the unit cell strings and the bit line, wherein only one unit cell string is connected to the bit line through one string selectors. The present invention can decrease a size of cell by eliminating a bit line contact formed in cells and controls a bit line capacitance by using selection transistor, therefore, the present invention can control optimum bit line capacitance by gaining the maximum sense margin.

Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device, the method including the steps of forming a unit die including a transistor and a capacitor on a semiconductor substrate, testing a wafer level function for the unit die, annealing the device above Curie temperature of ferroelectric material, and carrying out a package process for the device.

Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device, the method including the steps of forming a unit die including a transistor and a capacitor on a semiconductor substrate, testing a wafer level function for the unit die, annealing the device above Curie temperature of ferroelectric material, and carrying out a package process for the device.

Abstract: A ferroelectric memory cell for use in a ferroelectric random access memory (FeRAM) device that includes a first active area incorporating therein a gate of a depletion mode transistor, a second active area adjacent to the first active area and incorporating therein a gate of an enhancement mode transistor, a word line coupled to the gate of the depletion mode transistor and the gate of the enhancement mode transistor, and a ferroelectric capacitor coupled to a drain of the enhancement mode transistor, for storing data.

Abstract: Provided is a method for forming a ferroelectric capacitor of a semiconductor, which prevents the breakdown of a ferroelectric film induced from the out-diffusion of ingredients of the ferroelectric film. Using a thin film of SBT or Bi2O3 as a diffusion barrier layer capping the SBT ferroelectric film can prevent the breakdown of the ferroelectric film induced from the subsequently proceeded thermal treatment process at high temperature. As a result, the invention can decrease the fatigue of the device and enhance margin in the processes and the reliability of the device.