Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.

Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.

Abstract: A data storage device and fabrication and control methods thereof are disclosed. The data storage device includes a first-first sub-block of memory cells, a second-first sub-block of memory cells, a first well switch, a second well switch and a first group of word lines. The first well switch is operative to convey a first well bias to bias the first-first sub-block of memory cells. The second well switch is operative to convey a second well bias to bias the second-first sub-block of memory cells. Further, the first-first and the second-first sub-blocks both are activated according to the first group of word lines.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Abstract: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Abstract: Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

Abstract: To control the problem of program and erase disturb in flash memory arrays having multiple sectors of cells grouped in each isolation wells of the flash memory array, a refresh procedure is used that involves two readings of each of the cells in a “refresh area” of a group under different read timing conditions, with other read conditions being constant or varied as desired. Cells that yield the same result in both reads are not excessively disturbed and need not be reprogrammed. However, cells that read differently may be excessively disturbed and should be reprogrammed. The refresh procedure is particularly suitable for memory arrays with small sector size and many sectors per group. The memory arrays preferably incorporate memory cells that use hot electron programming and Fowler-Nordheim erase.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: To control the problem of program and erase disturb in flash memory arrays having multiple sectors of cells grouped in each isolation wells of the flash memory array, a refresh procedure is used that involves two readings of each of the cells in a “refresh area” of a group under different read timing conditions, with other read conditions being constant or varied as desired. Cells that yield the same result in both reads are not excessively disturbed and need not be reprogrammed. However, cells that read differently may be excessively disturbed and should be reprogrammed. The refresh procedure is particularly suitable for memory arrays with small sector size and many sectors per group. The memory arrays preferably incorporate memory cells that use hot electron programming and Fowler-Nordheim erase.

Abstract: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.