Abstract: A semiconductor device includes a substrate, an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns above an upper surface of the lower pattern and spaced apart from the lower pattern in a second direction substantially perpendicular to the first direction, a gate structure on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film at least partially surrounding the plurality of sheet patterns, a first gate capping pattern on the gate structure and above the plurality of sheet patterns in the second direction, a gate spacer extending along a side wall of the gate structure, and a second gate capping pattern extending along an upper surface of the gate structure and an upper surface of the first gate capping pattern.

Abstract: An integrated circuit device includes fin-type active regions protruding from a substrate and extending lengthwise in a first horizontal direction, source/drain regions respectively arranged on the fin-type active regions, a device isolation film covering both sidewalls of each fin-type active region, an insulating structure covering the source/drain regions and the device isolation film, source/drain contacts respectively arranged on and connected to the source/drain regions and apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a contact isolation insulating film arranged between the source/drain contacts in the second horizontal direction and having a lower surface closer to the substrate than a lower surface of each source/drain contact. At least one of the source/drain contacts includes a first portion extending in a vertical direction toward the substrate along a surface of the contact isolation insulating film.

Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor structure and a dummy structure on a substrate; forming a first insulating layer between the semiconductor structure and the dummy structure; forming a first space by removing the dummy structure; forming an isolation pattern in the first space; forming a main gate sacrificial pattern crossing the first direction to overlap the semiconductor structure; forming second spaces by removing portions of the semiconductor structure at both sides of the main gate sacrificial pattern, and forming source/drain patterns in the second spaces; forming a second insulating layer on the source/drain patterns; forming a third space by removing the main gate sacrificial pattern, and forming a gate electrode in the third space; and forming fourth spaces by removing the second insulating layer, and forming, in the fourth spaces, contact structures connected to the source/drain patterns and disposed on both sides of the isolation pattern.

Abstract: An integrated circuit device includes a first fin-type active region and a second fin-type active region, a device isolation film adjacent to each of the first and second fin-type active regions, a first gate line on the first fin-type active region, a second gate line on the second fin-type active region, and a gate cut insulating pattern separating the first and second gate lines, wherein the device isolation film includes a first local isolation portion and a second local isolation portion, which are separating the first fin-type active region from the second fin-type active region to be apart from each other with the gate cut insulating pattern therebetween.

Abstract: An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.

Abstract: A semiconductor package includes a first redistribution wiring layer having first redistribution wirings, a first semiconductor chip on the first redistribution wiring layer and having a first thickness from the first redistribution wiring layer, a second semiconductor chip disposed on the first redistribution wiring layer spaced apart from the first semiconductor chip and having a second thickness from the first redistribution wiring layer smaller than the first thickness, a sealing member covering the first semiconductor chip and the second semiconductor chip on the first redistribution wiring layer, a plurality of conductive vias provided in the sealing member and electrically connected to the first redistribution wirings, a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the conductive vias, and at least one third semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the secon

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, a chip connection terminal configured to electrically connect the first semiconductor chip to the second semiconductor chip, an underfill layer disposed between the first semiconductor chip and the second semiconductor chip and surrounding the chip connection terminal, a vertical porous structure filling spaces of a plurality of vertical cooling channels passing through the first semiconductor chip, the second semiconductor chip, and the underfill layer in a vertical direction, and having a plurality of cooling holes, and a cooling fluid provided to the plurality of cooling holes of the vertical porous structure to flow inside the plurality of vertical cooling channels.

Abstract: A semiconductor package is provided. The semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip, and including an upper wiring layer; a first connection structure disposed on the lower wiring layer, and having a first hollow open toward the upper substrate; a second connection structure disposed below the upper wiring layer, and having a second hollow open toward the lower substrate; a conductive connection member disposed between the first connection structure and the second connection structure, and filling at least a portion of the first hollow; and an encapsulant disposed between the lower substrate and the upper substrate, and encapsulating at least a portion of each of the semiconductor chip, the first connection structure and the second connection structure.