Abstract: A semiconductor device includes a channel layer, a gate electrode facing the channel layer, a gate insulating layer between the channel layer and the gate electrode, and a source electrode and a drain electrode electrically connected to the channel layer. The channel layer includes a semiconductor material having a two-dimensional crystal structure, and the gate insulating layer includes a three-dimensional bulk paraelectric material including zirconium oxide and an oxide of a metal having a valence of +3 or +4.

Abstract: The present invention relates to a 3-((8-((1H-pyrazol-4-yl)amino)imidazo[1,2-a]pyridin-3-yl)ethynyl)-N-phenylbenzamide derivative, a method for preparing the same, and a pharmaceutical composition comprising the same as an active ingredient for preventing or treating cancer. The derivative can significantly inhibit the proliferation of cancer cells by inhibiting kinases, particularly Bcr-Abl kinase or Bcr-Abl (T315I) kinase. Therefore, the derivative can be effectively used as a pharmaceutical composition for the prevention or treatment of cancer.

Abstract: A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

Abstract: A semiconductor device includes a channel layer including a van der Waals material, a source electrode structure and a drain electrode structure electrically connected to opposite ends of the channel layer, respectively, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer, wherein each of the source electrode structure and the drain electrode structure includes an interlayer including a dopant and one of a semiconductor or an insulator, and a metal layer on the interlayer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a two-dimensional material layer on a substrate; and supplying an etchant to the two-dimensional material layer to remove a residue from the two-dimensional material layer. The supplying the etchant to the two-dimensional material layer includes: supplying a first process gas to a chamber in which the substrate is provided; supplying microwaves to the chamber to form a first plasma in the chamber; and supplying a second process gas, including a different material from the first process gas, to the chamber to form a second plasma including the etchant.

Abstract: A semiconductor device includes a channel including a two-dimensional semiconductor material, a source electrode and a drain electrode electrically connected to both ends of the channel, respectively, a two-dimensional material oxide layer on the channel, a dipole oxide layer on the two-dimensional material oxide layer, a dielectric layer on the dipole oxide layer, and a gate electrode on the dielectric layer.

Abstract: A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

Abstract: Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/?m2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Abstract: Provided are semiconductor devices including vertically stacked semiconductor elements, methods of manufacturing the same, and electronic devices including the same. The semiconductor device includes a first semiconductor element formed in a front-end-of-line process, a second semiconductor element formed in a back-end-of-line process, and an interlayer insulating layer provided between the first and second semiconductor elements and including an internal via structure connecting the first and second semiconductor elements to each other. The internal via structure includes a layer structure through which an upper surface of a first material layer and a lower surface of a second material layer are connected to each other.

Abstract: Provided are a semiconductor device including a two-dimensional material and a manufacturing method thereof. The semiconductor device includes a channel layer containing a two-dimensional semiconductor material, a source electrode and a drain electrode provided on both sides of the channel layer, respectively, a gate insulating layer provided on the channel layer between the source electrode and the drain electrode and including a two-dimensional insulating material, an interlayer provided between the channel layer and the gate insulating layer, and a gate electrode provided on the gate insulating layer.

Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.

Abstract: A semiconductor device may include a substrate, a vertical channel, a gate electrode, and a conductive layer. The vertical channel may have a tube shape extending in a direction perpendicular to a surface of the substrate. The gate electrode may face the vertical channel with an outer insulating layer therebetween on an outer circumferential surface of the vertical channel. The conductive layer may face the vertical channel with an inner insulating layer therebetween on an inner circumferential surface of the vertical channel.

Abstract: A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a source electrode provided on a substrate, a drain electrode disposed away from the source electrode, and a channel connected between the source electrode and the drain electrode, wherein the channel includes a plurality of first channel layers and plurality of second channel layers, and the gate electrode is provided on one surface and another surface of each of the plurality of the first channel layers and on one surface and another surface of each of the plurality of the second channel layers.

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.