Abstract: A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.

Abstract: A display device according to an embodiment of the present disclosure comprises a display panel including a display area having a plurality of pixels connected to a plurality of gate lines, a gate driving circuit in a non-display area adjacent to the display area and including a plurality of stages supplying a gate signal to the plurality of gate lines, and an auxiliary load connected to at least one stage of the plurality of stages in the non-display area in which a number of the plurality of pixels which are connected to at least two gate lines among the plurality of gate lines varies. Therefore, the load applied to the output node of the gate driving circuit is uniformly adjusted so that a screen abnormality of the display device may be suppressed.

Abstract: A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.

Abstract: A display device according to an embodiment of the present disclosure comprises a display panel including a display area having a plurality of pixels connected to a plurality of gate lines, a gate driving circuit in a non-display area adjacent to the display area and including a plurality of stages supplying a gate signal to the plurality of gate lines, and an auxiliary load connected to at least one stage of the plurality of stages in the non-display area in which a number of the plurality of pixels which are connected to at least two gate lines among the plurality of gate lines varies. Therefore, the load applied to the output node of the gate driving circuit is uniformly adjusted so that a screen abnormality of the display device may be suppressed.

Abstract: Embodiment relate to a display panel that modulates 3D image data based on pixel data of adjacent lines. The display panel includes data lines, gate lines, and a plurality of pixels; a data modulation unit. The modulation unit modulates kth pixel data of a jth line in 3D image data based on the kth pixel data of the jth line and kth pixel data of a line adjacent to the jth line. The data driving circuit converts the modulated 3D image data into analog data voltages and outputs the analog data voltages to the data lines. A gate driving circuit sequentially outputs gate pulses to the gate lines.

Abstract: A stereoscopic image display device according to an exemplary embodiment of the present invention comprises: a display panel comprising data lines, gate lines, and a plurality of pixels; a data modulation unit that outputs modulated 3D image data by modulating kth pixel data of a jth line based on the kth pixel data of the jth line and kth pixel data of a line adjacent to the jth line; a data driving circuit that converts the modulated 3D image data into analog data voltages and outputs the analog data voltages to the data lines; and a gate driving circuit that sequentially outputs gate pulses to the gate lines.