Patents by Inventor EunNaRa Cho

EunNaRa Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210047172
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Patent number: 10822226
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 3, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Publication number: 20200251422
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.
    Type: Application
    Filed: April 24, 2020
    Publication date: August 6, 2020
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Young Woo LEE, Jae Ung LEE, Byong Jin KIM, EunNaRa CHO, Ji Hoon OH, Young Seok KIM, Jin Young KHIM, Tae Kyeong HWANG, Jin Seong KIM, Gi Jung KIM
  • Publication number: 20190152770
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: YungWoo Lee, ByungJun Kim, DongHyun Bang, EunNaRa Cho, Adrian Arcedera, JaeUng Lee
  • Publication number: 20180374798
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.
    Type: Application
    Filed: June 24, 2017
    Publication date: December 27, 2018
    Applicant: Amkor Technology, Inc.
    Inventors: Young Woo LEE, Jae Ung LEE, Byong Jin KIM, EunNaRa CHO, Ji Hoon OH, Young Seok KIM, Jin Young KHIM, Tae Kyeong HWANG, Jin Seong KIM, Gi Jung KIM
  • Publication number: 20180350734
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 10144634
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 4, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
  • Patent number: 10032705
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: May 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20180134546
    Abstract: Disclosed is a semiconductor device including a conductive shield layer formed within a cavity of a molding part and a manufacturing method thereof. Various aspects of the present invention, for example and without limitation, includes a semiconductor device including a conductive shield layer formed along the wall of a cavity to of a molding part to improve EMI shielding performance, and a manufacturing method thereof.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Ji Hoon Oh, Byong Jin Kim, Jin Young Kim, Young Seok Kim, EunNaRa Cho, Yung Woo Lee, Do Hyun Na
  • Publication number: 20180057353
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 1, 2018
    Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
  • Publication number: 20170320723
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 9, 2017
    Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
  • Patent number: 9809446
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: November 7, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
  • Publication number: 20170018493
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Application
    Filed: May 8, 2016
    Publication date: January 19, 2017
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20160221820
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 4, 2016
    Inventors: YungWoo Lee, ByungJun Kim, DongHyun Bang, EunNaRa Cho, Adrian Arcedera, JaeUng Lee
  • Publication number: 20150274511
    Abstract: Methods and systems for a semiconductor package may comprise a package device comprising at least one semiconductor chip and an active element attached to a substrate and a window with sidewalls forming cavity regions for the package device and coupled to the substrate with an adhesive. An outer edge of the substrate may be flush with an outer surface of the window sidewalls. The window may be plastic and may include an EMI shielding layer, which may be a copper/nickel plating layer. The semiconductor chip may be a MEMS microphone device. The sidewalls and a top plate of the window may be at a right angle to each other. The package may be formed by severing it from an N×M array of package structures resulting in the outer edges being flush.
    Type: Application
    Filed: June 15, 2015
    Publication date: October 1, 2015
    Inventors: Jong Dae Jung, Dong Hyun Bang, Yung Woo Lee, EunNaRa Cho, Byung Jun Kim
  • Patent number: 9056765
    Abstract: Various aspects of the present invention, for example and without limitation, comprise a semiconductor device package and/or method for manufacturing a semiconductor device package. Such a device package may, for example, comprise a MEMS device package.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: June 16, 2015
    Inventors: Jong Dae Jung, Dong Hyun Bang, Yung Woo Lee, EunNaRa Cho, Byung Jun Kim
  • Patent number: 9018741
    Abstract: A semiconductor package is presented which has a suitable structure for effectively shielding electromagnetic wave interference (EMI) in a cavity area to which a semiconductor chip is attached. The semiconductor package is assembled such that a lower substrate to which the semiconductor chip is attached is adhered to an EMI shielding & electric I/O body having various types of EMI shielding & electric I/O metal patterns by soldering. Further, the EMI shielding & electric I/O body is adhered to an upper substrate by soldering thereby simplifying assembling of the semiconductor package.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 28, 2015
    Inventors: Dong In Kim, Jae Ung Lee, Eunnara Cho, Min Ju Kim
  • Publication number: 20140017843
    Abstract: Various aspects of the present invention, for example and without limitation, comprise a semiconductor device package and/or method for manufacturing a semiconductor device package. Such a device package may, for example, comprise a MEMS device package.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 16, 2014
    Inventors: Jong Dae Jung, Dong Hyun Bang, Yung Woo Lee, EunNaRa Cho, Byung Jun Kim