Patents by Inventor Eun-Suk Kang
Eun-Suk Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966919Abstract: Various example embodiments of the disclosure relate to an electronic device and a wireless communication connection control method thereof.Type: GrantFiled: March 14, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Ho Kang, Jinhyun Park, Ye-Ji Yoon, Jun-Hak Lim, Wontae Chae, Jongmu Choi, Bokun Choi, Doo-Suk Kang, Sun-Kee Lee, Moonsoo Kim, Eun Jung Hyun
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Patent number: 11961679Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.Type: GrantFiled: November 2, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Eun Jung Lee, Jong Suk Jeong, Chun Hee Seo, Jong Hoon Yoo, Tae Hyung Kim, Ho Sam Choi, Sim Chung Kang
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Publication number: 20240101810Abstract: The present invention relates to a composition for forming a composite polymer film, a method for preparing the composition for forming a composite polymer film, a composite polymer film and a method for preparing the composite polymer film. The composition for forming a composite polymer film comprises: a fluorine-based polymer solution comprising a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the fluorine-based polymer solution. The method for preparing the composition for forming a composite polymer film comprises the steps of: preparing a fluorine-based polymer solution comprising a fluorine-based polymer; and dispersing polyvinylidene fluoride nanoparticles in the fluorine-based polymer solution. The composite polymer film comprises: a polymer matrix formed from a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the polymer matrix.Type: ApplicationFiled: September 4, 2020Publication date: March 28, 2024Applicants: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY, KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Eun Ho SOHN, Shin Hong YOOK, Hong Suk KANG, In Joon PARK, Sang Goo LEE, Soo Bok LEE, Won Wook SO, Hyeon Jun HEO, Dong Je HAN, Seon Woo KIM
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Publication number: 20220221462Abstract: The present invention relates to a marker for diagnosing colorectal cancer, a method for providing information required for the diagnosis of colorectal cancer by using same, and a method for providing information for monitoring the response to colorectal cancer therapy by using same.Type: ApplicationFiled: April 29, 2020Publication date: July 14, 2022Inventors: Eun Suk KANG, Hee Cheol KIM, Jae Won YUN
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Patent number: 7885141Abstract: Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The configuration controller can be configured to set configuration information in the configuration register based on the state of a select flag stored in the nonvolatile memory cell array. The nonvolatile memory device can be configured to maintain the configuration information using the select flag and a lock flag to prevent the configuration information from changing when security is utilized and reduce the likelihood of the nonvolatile memory device operating erroneously.Type: GrantFiled: December 8, 2006Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Eun-suk Kang
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Patent number: 7751276Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.Type: GrantFiled: December 4, 2008Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Suk Kang, So-Hoe Kim
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Patent number: 7698615Abstract: A semiconductor memory device that performs an error control operation when an error exists in an externally received command or an externally received address, and a method of driving the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array having a single-level cell area and a multi-level cell area, a command decoder which receives a command from an external source and decoding the command, an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area, a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result, and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signal.Type: GrantFiled: August 14, 2007Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-suk Kang, Young-joon Choi, Sang-kil Lee, Dae-hyun Lee
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Patent number: 7689741Abstract: A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.Type: GrantFiled: September 13, 2004Date of Patent: March 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Suk Kang, Jin-Yub Lee
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Publication number: 20090086566Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.Type: ApplicationFiled: December 4, 2008Publication date: April 2, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Suk KANG, So-Hoe KIM
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Patent number: 7477569Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.Type: GrantFiled: December 27, 2005Date of Patent: January 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Suk Kang, So-Hoe Kim
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Publication number: 20080141100Abstract: A semiconductor memory device that performs an error control operation when an error exists in an externally received command or an externally received address, and a method of driving the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array having a single-level cell area and a multi-level cell area, a command decoder which receives a command from an external source and decoding the command, an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area, a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result, and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signal.Type: ApplicationFiled: August 14, 2007Publication date: June 12, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-suk Kang, Young-joon Choi, Sang-kil Lee, Dae-hyun Lee
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Publication number: 20080126735Abstract: Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The configuration controller can be configured to set configuration information in the configuration register based on the state of a select flag stored in the nonvolatile memory cell array. The nonvolatile memory device can be configured to maintain the configuration information using the select flag and a lock flag to prevent the configuration information from changing when security is utilized and reduce the likelihood of the nonvolatile memory device operating erroneously.Type: ApplicationFiled: December 8, 2006Publication date: May 29, 2008Inventor: Eun-suk Kang
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Publication number: 20070028037Abstract: A memory device having a dual buffering scheme between a host and a memory core may include an address generator to automatically generate first and second addresses in response to an initial buffer-sector address. The host may access the dual buffer in response to the first address, while the memory core may simultaneously access the dual buffer in response to the second address.Type: ApplicationFiled: May 12, 2006Publication date: February 1, 2007Applicant: Samsung Electronics Co., Ltd.Inventor: Eun-Suk KANG
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Publication number: 20060164910Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.Type: ApplicationFiled: December 27, 2005Publication date: July 27, 2006Inventors: Eun-Suk Kang, So-Hoe Kim
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Publication number: 20050060486Abstract: A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.Type: ApplicationFiled: September 13, 2004Publication date: March 17, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-Suk Kang, Jin-Yub Lee