Abstract: A semiconductor memory device capable of reducing current consumption in a partial-array self-refresh (PASR) mode includes a plurality of banks and at least one parity bank. A specific area to be self-refreshed is individually selected from each of some banks selected out of the plurality of banks to perform a self-refresh operation. Data of the specific area to be self-refreshed is verified using an error correction code (ECC) stored in the parity bank.

Abstract: A projection system is characterized by: a first light source unit and a second light source unit selectively driven in response to operation mode; a light transmitting unit transmitting light emitted from the first light source unit or the second light source unit in the form of surface light; an image generator generating an image in response to an image signal using the light transmitted from the light transmitting unit; and a projection lens system projecting the image by enlarging the image generated by the image generator and projecting the enlarged image.

Abstract: Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.

Abstract: A projection system is disclosed, the projection system including: an illumination unit; a PBS (Polarizing Beam Splitter) reflecting the light from the illumination unit, transmitting an image light, having a width larger than that of entrance pupil through which the image light is incident, and having a structure in which a width of an area facing projection lenses is larger than that of an area perpendicular to an area facing the projection lenses; a display device receiving the light reflected from the PBS and outputting the light as an image light; and a projection unit mounted with the projection lenses for projecting the image light outputted from the display device to a screen.

Abstract: Disclosed is a polarization conversion apparatus, the apparatus including a first optical device capable of angle-converting incident unpolarized light to allow a polarization direction to be emitted in mutually different first and second linear polarizations, an FEL (Fly Eye Lens) including first and second MLAs (Micro Lens Arrays) arrayed with first and second micro lenses, where first and second linear polarizations of the first optical device incident on the first micro lenses are divided and condensed on an upper side and a bottom side of the second micro lenses of the second MLA, and a second optical device converting the first and second linear polarizations condensed on the upper side or the bottom side of the second MLA at the FEL to any one polarization of the first and second linear polarizations and emitting the polarization.

Abstract: Disclosed is a projector optical system, the system including an illumination unit including illumination lenses illuminating light downwards, a display device receiving light illuminated from the illumination lenses to enable to realize an image, projection lenses downwardly projecting light emitted from the display device to a screen, and a field lens changing an optical angle of the light illuminated from the illumination lenses and emitting the light to the display device, and changing an optical angle by receiving an image light of the display device and emitting the light to the projection lenses.

Abstract: Disclosed is a projector, the projector including a light source, an illumination unit illuminating light incident from the light source, and a display device enabling to realize an image by receiving the light irradiated from the illumination unit, and whose center is positioned at an axis different from an optical axis of the illumination unit.

Abstract: A semiconductor memory device capable of reducing current consumption in a partial-array self-refresh (PASR) mode includes a plurality of banks and at least one parity bank. A specific area to be self-refreshed is individually selected from each of some banks selected out of the plurality of banks to perform a self-refresh operation. Data of the specific area to be self-refreshed is verified using an error correction code (ECC) stored in the parity bank.

Abstract: The present disclosure relates to a polarization converting device and a method for manufacturing the same, wherein the polarization converting device includes a polarization separation unit aligned with a plurality of unit blocks including an optical separator transmitting a first polarization between an upper surface and a lower surface and reflecting a second polarization, and a phase retarder aligned in correspondence to an upper surface of each unit block of the polarization separation unit where a first region and a second region are alternately formed, wherein any one of the first and second regions of the phase retarder converts the polarized light while the other region emits the polarized light as it is.

Abstract: A semiconductor memory device and a refresh clock signal generator thereof are provided. The refresh clock signal generator of the semiconductor memory device includes a voltage generator for receiving a power voltage to generate a voltage which is lower than the power voltage; a ring oscillator enabled in response to a self refresh control signal, including an odd number of at least three inverters, having a first current consumption when a temperature of the semiconductor memory device is high and a second current consumption when the temperature is low, and generating a clock signal whose cycle is increased as the temperature is lowered; and a level shifter for converting the clock signal of the voltage which is lower than the power voltage into a refresh clock signal which has a level of the power voltage.

Abstract: A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy memory cell corresponding to the unprogrammed signal when the first redundancy enable signal from the first control unit or a second redundancy enable signal from the second control unit is activated. Thus, the redundancy memory cell access circuit is tested simultaneously with testing of the redundancy memory cell for minimized testing and programming times.

Abstract: Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.

Abstract: A semiconductor memory device and a refresh clock signal generator thereof are provided. The refresh clock signal generator of the semiconductor memory device includes a voltage generator for receiving a power voltage to generate a voltage which is lower than the power voltage; a ring oscillator enabled in response to a self refresh control signal, including an odd number of at least three inverters, having a first current consumption when a temperature of the semiconductor memory device is high and a second current consumption when the temperature is low, and generating a clock signal whose cycle is increased as the temperature is lowered; and a level shifter for converting the clock signal of the voltage which is lower than the power voltage into a refresh clock signal which has a level of the power voltage.

Abstract: Method and apparatus for use with internal array voltage generators in semiconductor memory devices are disclosed. In one described embodiment, an overdriving level control circuit is used to generate an overdriving control signal for an internal array voltage generator driver, just prior to a sensing operation. The overdriving level control circuit uses a cell modeling circuit to estimate, just prior to the sensing operation, a current requirement for the sensing operation, and an amplifier to generate the overdriving control signal in response to the estimated current requirement. Such a design allows the amount of overdrive signal to track process, voltage, and temperature changes, for example, to provide an accurate overdrive that allows the internal array voltage to remain stable. Other embodiments are described and claimed.

Abstract: An electrical fuse circuit may include at least one contact plug and a fusing select control unit. The at least one contact plug may couple a wiring layer of a semiconductor device to an active region of a transistor device. The fusing select control unit may cause a latch-up phenomenon in response to an applied signal so that selected ones of the at least one contact plugs are fused by over-current due to the latch-up phenomenon.

Abstract: Method and apparatus for use with internal array voltage generators in semiconductor memory devices are disclosed. In one described embodiment, an overdriving level control circuit is used to generate an overdriving control signal for an internal array voltage generator driver, just prior to a sensing operation. The overdriving level control circuit uses a cell modeling circuit to estimate, just prior to the sensing operation, a current requirement for the sensing operation, and an amplifier to generate the overdriving control signal in response to the estimated current requirement. Such a design allows the amount of overdrive signal to track process, voltage, and temperature changes, for example, to provide an accurate overdrive that allows the internal array voltage to remain stable. Other embodiments are described and claimed.