Patents by Inventor Eva-Maria Nash

Eva-Maria Nash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for searching for potential faults in a layout of an integrated circuit
    Patent number: 7484189
    Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: January 27, 2009
    Assignee: Qimonda AG
    Inventors: Markus Hofsäss, Eva-Maria Nash
  • Method for searching for potential faults in a layout of an integrated circuit
    Publication number: 20070044050
    Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.
    Type: Application
    Filed: August 18, 2006
    Publication date: February 22, 2007
    Applicant: QIMONDA AG
    Inventors: Markus Hofsass, Eva-Maria Nash