Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Abstract: Apparatus and methods are provided for enabling wafer-scale encapsulation of microelectromechanical (MEM) devices (e.g., resonators, filters) to protect the MEMs from the ambient and to provide either a controlled ambient or a reduced pressure. In particular, methods for wafer-scale encapsulation of MEM devices are provided, which enable encapsulation of MEM devices under desired ambient conditions that are not determined by the deposition conditions of a sealing process in which MEM release via holes are sealed or pinched-off, and which prevent sealing material from being inadvertently deposited on the MEM device during the sealing process.

Abstract: The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material (e.g., thermal paste), wherein a thermal interface is designed to prevent/inhibit the formation of voids in the compliant thermally conductive material due to the flow of such material in and out from between the chips and the heat conducting device due to thermal cycling.

Abstract: A cooling system for an electronic component on a component carrier is provided. The system includes a frame, a spray manifold, and a sealing member. The frame has an opening and is connectable to the component carrier so that an annular area is defined between the opening and the electronic component. The spray manifold is sealed over the opening to define a spray area over a back surface of the electronic component. The spray manifold sprays a cooling fluid on the back surface. The sealing member seals the annular region so that input/output connectors on the component carrier are isolated from the cooling fluid.

Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Abstract: A multiple power density packaging structure with two or more semiconductor chips on a common wiring substrate having a common thermal spreader with a planar surface in thermal contact with the non-active surfaces of the chips. The semiconductor chips have different cooling requirements and some of the chips are thinned to insure that the chips requiring the lowest thermal resistance has the thinnest layer of a thermal adhesive or metal or solder interface between the chip and thermal spreader.

Abstract: Apparatus and methods are provided for microchannel cooling of electronic devices such as IC chips, which enable efficient and low operating pressure microchannel cooling of high power density electronic devices. Apparatus for microchannel cooling include integrated microchannel heat sink devices and fluid distribution manifold structures that are designed to provide uniform flow and distribution of coolant fluid and minimize pressure drops along coolant flow paths.

Abstract: Apparatus and methods are provided for microchannel cooling of electronic devices such as IC chips, which enable efficient and low operating pressure microchannel cooling of high power density electronic devices having a non-uniform power density distribution, which are mounted face down on a package substrate. For example, integrated microchannel cooler devices (or microchannel heat sink devices) for cooling IC chips are designed to provide uniform flow and distribution of coolant fluid and minimize pressure drops along coolant flow paths, as well as provide variable localized cooling capabilities for high power density regions (or “hot spots”) of IC chips with higher than average power densities.

Abstract: A thermal interposer is provided for attachment to the back surface of a semiconductor device so as to give a very low thermal resistance. In one preferred embodiment, the thermal interposer has two plates containing wick structures such as grooves. The thermal interposer is integrated with a semiconductor device so as to form a vapor chamber. In particular, the back surface of the semiconductor chip is in direct contact with the interior sealed volume of the vapor chamber, so as to greatly reduce the thermal resistance from the combination of the chip and the vapor chamber. Further, the upper plate is thermally coupled to a heat-sinking fixture such as a heat sink or a cold plate.

Abstract: A thermal interposer is provided for attachment to a surface of a semiconductor device. In one embodiment, the thermal interposer includes an upper plate having a bottom surface with a plurality of grooves and made of a material having high thermal conductivity, and a lower plate having a top surface with a plurality of grooves and made of a material having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the material of a semiconductor device that is bonded to the bottom surface of the lower plate. The bottom surface of the upper plate is hermetically bonded to the top surface of the lower plate so that a vapor chamber is formed by the upper and lower plates, and walls of the grooves on the top surface of the lower plate extend to within less than 250 microns from walls of the grooves on the bottom surface of the upper plate comprise a plurality of second walls the first walls.

Abstract: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical stress due to the relative displacement due to the difference in thermal expansion between the semiconductor chip and the heat conducting device.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: In an integrated circuit packaging structure, such as in an MCM or in a SCM, a compliant thermally conductive material is applied between a heat-generating integrated circuit chip and a substrate attached thereto. Raised regions are defined on the back side of the chip aligned to areas of a higher than average power density on the front active surface of the chip such that a thinner layer of the compliant thermally conductive material is disposed between the chip and the substrate in this area after assembly thereof resulting in a reduced “hot-spot” temperature on the chip. In an exemplary embodiment, the substrate includes one of a heat sink, cooling plate, thermal spreader, heat pipe, thermal hat, package lid, or other cooling member.

Abstract: An optoelectronic assembly for an electronic system includes a support electronic chip set configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions. A first substrate having a first surface and an opposite second surface is in communication with the support electronic chip set via the first surface while a second substrate is in communication with the second surface of the first substrate. The second substrate is configured for mounting at least one of data processing, data switching and data storage chips. An optoelectronic transducer is in signal communication with the support electronic chip set and an optical fiber array is aligned at a first end with the optoelectronic transducer and with an optical signaling medium at a second end.

Abstract: An optoelectronic assembly for a computer system includes an electronic chip(s), a substrate, an electrical signaling medium, an optoelectronic transducer, and an optical coupling guide. The electronic chip(s) is in communication with the substrate, which is in communication with a first end of the electrical signaling medium. A second end of the electrical signaling medium is in communication with the optoelectronic transducer, and includes the optical coupling guide for aligning an optical signaling medium with the optoelectronic transducer. An electrical signal from the electronic chip is communicated to the optoelectronic transducer via the substrate and the electrical signaling medium. The optical transducer and electronic chip(s) share a common heat spreader, and communication to other groups of electronic chip(s) is done without the need for communication via a second level electrical package.

Abstract: A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal.

Abstract: A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal.

Abstract: The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C.