Abstract: A test circuit and apparatus that meets requirements of Human Body Model electrostatic discharge sensitivity testing of microelectronic components that can properly test high voltage and unconnected pins is disclosed. “No Connect” pins were exempted from HBM testing by some testing standards due to prior art testers producing unintended overstress. A HBM tester has been invented that reduces this overstressing to levels were valid testing of integrated circuit No Connect pins and pins with high voltage ESD clamping protection is possible.

Abstract: Systems and methods of applying repeatable stress pulses to an integrated circuit device under test using the charged device model (CDM) test is provided. The CDM spark conduction using discharge pin implemented in sections allows the spark environment to be controlled increasing the stress reproducibility and ability to apply the CDM test to devices with fine pitch terminals.

Abstract: An approach for transmission line pulse and very fast transmission line pulse reflection control is provided. The approach includes using a power splitter to split an incident pulse into two identical pulses with one going to a device under test (DUT) through a delivery cable and the other going down an open ended delay cable. The structure of the power splitter, along with having the delivery cable and the open ended delay cable with the same signal propagation time and pulse transmission characteristics enable the canceling of pulse reflections from the DUT.

Abstract: An approach for transmission line pulse and very fast transmission line pulse reflection control is provided. The approach includes using a power splitter to split an incident pulse into two identical pulses with one going to a device under test (DUT) through a delivery cable and the other going down an open ended delay cable. The structure of the power splitter, along with having the delivery cable and the open ended delay cable with the same signal propagation time and pulse transmission characteristics enable the canceling of pulse reflections from the DUT.

Abstract: This invention is an electrostatic discharge (ESD) testing circuit that can deliver current pulses to a component under test (CUT) with controlled impedance. Generated current pulses simulating ESD events, such as those compliant to the European International Electrotechnical Commission IEC 61000-4-2 standard, can be delivered to the CUT with low distortion through a constant impedance electrical path, such as a combination of cables and controlled impedance conductors of printed wiring boards and wafer probes compatible with packaged IC devices, assemblies, and wafers, plus an impedance controlling series resistance. The current pulse can be delivered to the CUT with various forcing impedances. Measurements of the current passing through the CUT can be made.

Abstract: This invention is an electrostatic discharge testing circuit that can deliver current pulses to a component under test (CUT) with a custom amplitude versus time profile shape. Pulse generation with customized shapes is accomplished by discharging an energy storage network comprised of capacitor(s), transmission line(s) and other passive components. Current pulses compliant to the European International Electrotechnical Commission IEC 61000-4-2 standard can be so produced. These current pulses are delivered to the CUT with low distortion through a constant impedance electrical path, such as a combination of cables and controlled impedance conductors of printed wiring boards compatible with packaged IC devices, assemblies, and wafer probes. The current pulses can be delivered with various impedances, and measurements made that allow the CUT currents and voltages to be calculated.

Abstract: This invention generates two pulses for semiconductor testing that have leading edges coordinated in time by synchronizing the pulses from two different styles of pulse generators (pulsers). One pulser uses spark discharge pulse generation and the other pulser is a typical solid state pulser. The spark discharge pulser has high power pulse generation but its pulse timing can not be tightly controlled. The output pulse of the spark discharge pulser is split unequally, with a small amount used to trigger the solid state pulser, and the large pulse energy delayed by a cable of length for a signal propagation delay equal or greater than the trigger-input-to-pulse-output delay of the solid state pulser. Variable attenuators control the trigger signal amplitude and a level shifting circuit makes the trigger signal compatible with standard logic signal levels. The two pulses can be applied to semiconductors with their leading edges adjustable relative to each other to measure the semiconductors operation.

Abstract: This invention generates two pulses for semiconductor testing that have leading edges coordinated in time by synchronizing the pulses from two different styles of pulse generators (pulsers). One pulser uses spark discharge pulse generation and the other pulser is a typical solid state pulser. The spark discharge pulser has high power pulse generation but its pulse timing can not be tightly controlled. The output pulse of the spark discharge pulser is split unequally, with a small amount used to trigger the solid state pulser, and the large pulse energy delayed by a cable of length for a signal propagation delay equal or greater than the trigger-input-to-pulse-output delay of the solid state pulser. Variable attenuators control the trigger signal amplitude and a level shifting circuit makes the trigger signal compatible with standard logic signal levels. The two pulses can be applied to semiconductors with their leading edges adjustable relative to each other to measure the semiconductors operation.

Abstract: A new circuit for producing simulated electrostatic discharges (ESD) based on the Human Body Model (HBM) is disclosed for testing integrated circuits. HBM ESD test systems provide stress pulses defined by industry standards. The pulses produced by prior art have small imperfections or anomalies. These anomalies can cause incorrect testing to certain devices. The improved ESD HBM test system herein disclosed provides pulses meeting the requirements of industry standards while reducing several anomalies to negligible levels.

Abstract: A Transmission Line Pulse (“TLP”) measurement system for testing devices such as integrated circuits (“ICs”), and especially for testing the electrostatic discharge (“ESD”) protection structures connected to terminals on such ICs. The TLP measurement system measures the pulsed voltage and/or current of a device under test (“DUT”) by recording voltage and/or current pulse waveforms traveling in a constant impedance cable to and from the DUT. The pulses going to and returning from the DUT are processed to create signal replicas of the voltage and current pulses that actually occurred at the DUT. Oscilloscope operating settings optimize the recording of these signal replicas by improving the measurement signal-to-noise ratio. This improved TLP system is especially useful when very short width pulses on the order of less than 10 nanoseconds are used to test the DUT's response.

Abstract: This invention is an electrostatic discharge testing circuit that can deliver current pulses to a component under test (CUT) with a custom amplitude versus time profile shape. Pulse generation with customized shapes is accomplished by discharging an energy storage network comprised of capacitor(s), transmission line(s) and other passive components. Current pulses compliant to the European International Electrotechnical Commission IEC 61000-4-2 standard can be so produced. These current pulses are delivered to the CUT with low distortion through a constant impedance electrical path, such as a combination of cables and controlled impedance conductors of printed wiring boards compatible with packaged IC devices, assemblies, and wafer probes. The current pulses can be delivered with various impedances, and measurements made that allow the CUT currents and voltages to be calculated.

Abstract: A Transmission Line Pulse (TLP) testing system is disclosed that has a negative pulse inverter circuit that prevents large negative reflections which typically occur after the initial TLP pulse is applied to a low impedance device under test (DUT). Avoiding repetitive reflections, which naturally occur in TLP systems, prevents inducing DUT damage and confusing testing results. The pulse inverter circuit reduces reflections to lower levels than prior art TLP configurations, and can also be combined with known techniques to further reduce reflections for different impedance DUTs.

Abstract: A transmission Line Pulse (TLP) device calibration method wherein the TLP device includes a pulse generator for generating a pulse, a cable having an input terminal coupled to said pulse generator, an output terminal, and at least one ground return terminal, for coupling said pulse to a device under test (DUT) when it is connected to said output terminal, and a sensor for sensing the voltage and current at a selected point in said cable to measure the pulsed voltage and current of the DUT as the pulses travel in the cable to and from the DUT.

Abstract: A transmission Line Pulse (TLP) device calibration method wherein the TLP device includes a pulse generator for generating a pulse, a cable having an input terminal coupled to said pulse generator, an output terminal, and at least one ground return terminal, for coupling said pulse to a device under test (DUT) when it is connected to said output terminal, and a sensor for sensing the voltage and current at a selected point in said cable to measure the pulsed voltage and current of the DUT as the pulses travel in the cable to and from the DUT.

Abstract: A new circuit for producing simulated electrostatic discharges (ESD) based on the Human Body Model (HBM) is disclosed for testing integrated circuits. HBM ESD test systems provide stress pulses defined by industry standards. The pulses produced by prior art have small imperfections or anomalies. These anomalies can cause incorrect testing to certain devices. The improved ESD HBM test system herein disclosed provides pulses meeting the requirements of industry standards while reducing several anomalies to negligible levels.

Abstract: A Transmission Line Pulse (“TLP”) measurement system for testing devices such as integrated circuits (“ICs”), and especially for testing the electrostatic discharge (“ESD”) protection structures connected to terminals on such ICs. The TLP measurement system measures the pulsed voltage and/or current of a device under test (“DUT”) by recording voltage and/or current pulse waveforms traveling in a constant impedance cable to and from the DUT. The pulses going to and returning from the DUT are processed to create signal replicas of the voltage and current pulses that actually occurred at the DUT. Oscilloscope operating settings optimize the recording of these signal replicas by improving the measurement signal-to-noise ratio. This improved TLP system is especially useful when very short width pulses on the order of less than 10 nanoseconds are used to test the DUT's response.

Abstract: This invention discloses an apparatus for measuring an ion-implantation ion energy and/or dosage. The apparatus includes a scanning densitometer for measuring a reflected light from a monitor substrate. The apparatus further uses a monitor substrate. A thin film is supported on the monitor substrate wherein the thin film has an optical characteristic that is sensitive to the ion-implantation. The apparatus further includes a light source for projecting a measuring beam onto the monitor substrate for generating a reflected light. The apparatus also includes a bare silicon substrate for measuring a full scale reflected light represented by I0 reflected from the bare silicon substrate with the light source projecting a full scale light onto the bare silicon substrate.

Abstract: A high-resolution and high-speed film thickness and thickness uniformity measurement method is disclosed in this invention. The disclosed method includes a step a) of measuring a film thickness at a single point on the top surface of the substrate using an interferometry with a measuring light beam having a range of wavelengths. The method further includes a step b) of selecting an optimal wavelength from the range of wavelengths applied for measuring the film thickness at the single point. The method further includes a step c) of measuring reflection intensities by scanning over a plurality of points with a measuring light beam of the optimal wavelength over the top surface of the substrate. The method further includes a step d) of calculating a film thickness at the plurality of points applying the optimal-wavelength reflection intensities at the plurality of points over the top surface of the substrate.

Abstract: This invention discloses an apparatus for measuring an ion-implantation ion energy and/or dosage. The apparatus includes a scanning densitometer for measuring a reflected light from a monitor substrate. The apparatus further uses a monitor substrate. A thin film is supported on the monitor substrate wherein the thin film has an optical characteristic that is sensitive to the ion-implantation. The apparatus further includes a light source for projecting a measuring beam onto the monitor substrate for generating a reflected light. The apparatus also includes a bare silicon substrate for measuring a full scale reflected light represented by I0 reflected from the bare silicon substrate with the light source projecting a full scale light onto the bare silicon substrate.

Abstract: A high-resolution and high-speed film thickness and thickness uniformity measurement method is disclosed in this invention. The disclosed method includes a step a) of measuring a film thickness at a single point on the top surface of the substrate using an interferometry with a measuring light beam having a range of wavelengths. The method further includes a step b) of selecting an optimal wavelength from the range of wavelengths applied for measuring the film thickness at the single point. The method further includes a step c) of measuring reflection intensities by scanning over a plurality of points with a measuring light beam of the optimal wavelength over the top surface of the substrate. The method further includes a step d) of calculating a film thickness at the plurality of points applying the optimal-wavelength reflection intensities at the plurality of points over the top surface of the substrate.