Abstract: A memory buffer device and memory module for accurate hot and cold page detection is disclosed. The memory buffer device is coupled to a device memory including a plurality of regions. The memory buffer device identifies frequently accessed regions of the plurality of regions by counting accesses to the plurality of regions at a first granularity. The frequently accessed regions are associated with counters that satisfy a threshold criterion and are further tracked using a filter at a second granularity. The second granularity is smaller than the first granularity.

Abstract: Technologies for configurable adaptive double device data correction (ADDDC) are described. A memory buffer device includes error detection and correction (EDC) logic to autonomously detect errors in a region of memory and, upon detection of an error, calculate additional ECC check symbols for cache lines in the region and store the additional ECC check symbols as metadata associated with the cache lines.

Abstract: Disclosed are techniques for a memory buffer to track access to paged regions of a memory system at a configurable granularity finer than the size of the paged regions to provide more detailed statistics on memory access. The memory buffer may advertise its capabilities for fine-grained cold page tracking. The memory buffer may receive from the host information to configure a granularity of sub-regions of a paged region and a size of counters used to track access to the sub-regions. The memory buffer may track access requests to the sub-regions using the counters and to provide information on sub-region tracking to the host to identify individual hot or cold sub-regions. The host may make migration decisions for the paged regions with more granular information such as compaction of sub-regions to create a cold page or to treat each sub-region as a separately compressible entity to compress a mostly cold page.

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

Abstract: A memory system enables a host device to flexibly allocate compressed storage managed by a memory buffer device. The host device allocates a first block of host-visible addresses associated with the compressed region and a memory buffer device allocates a corresponding second block of host-visible memory. The host device may migrate uncompressed data to and from compressed storage by referencing an address in the second block (with compression and decompression managed by the memory buffer device) and may migrate compressed data to and from compressed storage (bypassing compression and decompression on the memory buffer device) by instead referencing an address in the first block.

Abstract: Described are computational systems in which hosts share pooled memory on the same memory module. A memory buffer with access to the pooled memory manages which regions of the memory are allocated to the different hosts such that memory regions, and thus the data they contain, can be exchanged between hosts. Unidirectional or bidirectional data exchanges between hosts swap regions of equal size so the amount of memory allocated to each host is not changed as a result of the exchange.

Abstract: A memory system selectively compresses and/or decompresses pages of a memory array based on requests from a host device. Upon performing compression, the memory buffer device returns compression context metadata to the host device for storing in the page table of the host device to enable the host device to subsequently obtain data from the compressed page. The host device may subsequently send a request for the memory buffer device to perform decompression to a free page in the memory array for accessing by the host device, or the host device may directly access the compressed page for local decompression and storage.

Abstract: Techniques for providing reduced latency metadata encryption and decryption are described herein. A memory buffer device having a cryptographic circuit to receive a first data and a first metadata associated with the first data. The cryptographic circuit can encrypt or decrypt the first metadata using a first cryptographic algorithm. The cryptographic circuit can encrypt or decrypt the first data using a second cryptographic algorithm. The first data and the first metadata can be stored at a same location, within a memory device, corresponding to a memory address.

Abstract: A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.

Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

Abstract: Systems and techniques for cryptographically protecting data in a computer memory are disclosed. The techniques include dividing the data into a first portion and a second portion, encrypting the first portion of the data to create a first stored form of the data, encrypting the second portion of the data, and storing, in the computer memory, the first stored form of the data and a second stored form of the data. The techniques include, to encrypt the second portion, calculating a hash based on the first stored form of the data, applying a first pseudorandom function to the hash to obtain a bit sequence, and combining the bit sequence with the second portion of the data to obtain the second stored form of the data.

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

Abstract: Head-mounted display assemblies may include a first eyecup and a second eyecup that are configured for respectively positioning a first lens and a second lens in front of intended locations of a user's eyes when the head-mounted display assembly is donned. The first eyecup and the second eyecup may be movable relative to each other to adjust for an interpupillary distance of the user's eyes. A single near-eye display screen may be configured for displaying an image to the user through the first and second eyecups. An enclosure over the single near-eye display screen may include a first transparent component positioned between the first lens and the single near-eye display screen and a second transparent component positioned between the second lens and the single near-eye display screen. Various other methods, devices, systems, and assemblies are also disclosed.

Abstract: An adjustment system includes: a first strap assembly and a second strap assembly positioned 180 degrees with respect to, and entwined with, the first strap assembly. Each strap assembly includes a slider having first and second slots therein. The slots are defined, in-part, by a central portion extending between both of the slots, a first end portion extending along the first slot opposite the central portion, and a second end portion extending along the second slot opposite the central portion. Each strap assembly further includes a strap portion having a first end coupled to the second end portion of the slider and an opposite second end structured to be coupled to one or more of the patient interface device or another portion of the headgear; and a tab coupled to the first end portion of the slider, the tab being structured to be grasped by the patient.

Abstract: An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a read command to retrieve read data from a memory. Memory interface circuitry couples to the memory. Data freshness authentication circuitry performs a freshness verification operation on the read data. Read data forwarding circuitry, in a skid mode of operation, transmits the read data to the host prior to completion of the freshness verification operation.

Abstract: A memory buffer device facilitates secure read and write operations associated with data that includes a predefined data pattern. For read operations, the memory buffer device detects a read data pattern in the read data that matches a predefined data pattern. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic for communicating the metadata in encrypted form.

Abstract: Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.