Patents by Inventor Evan M. Fledell

Evan M. Fledell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10677845
    Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Abram M. Detofsky, Evan M. Fledell, Mustapha A. Abdulai, John M. Peterson, Dinia P. Kitendaugh, Pooya Tadayon, Jin Pan, David Shia
  • Patent number: 10278302
    Abstract: Techniques and mechanisms for providing socket connection to a substrate. In an embodiment, a socket device includes a first socket body portion that is to provide for signal exchanges as part of a socket connector including the first socket body portion and a second socket body portion. The first socket body portion and the second socket body portion comprise respective zones, wherein, of the two zones, only one such zone has a first electro-mechanical characteristic. The first electro-mechanical characteristic is selected from the group consisting of an interconnect dimension, an interconnect material, an interconnect structure, a socket body material, and a shielding structure. In another embodiment, modular socket sub-assemblies each comprise a respective one of the first zone and the second zone.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Anne M. Sepic, Zhen Zhou, Evan M. Fledell
  • Publication number: 20180252772
    Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Applicant: Intel Corporation
    Inventors: Abram M. Detofsky, Evan M. Fledell, Mustapha A. Abdulai, John M. Peterson, Dinia P. Kitendaugh, Pooya Tadayon, Jin Pan, David Shia
  • Publication number: 20170187133
    Abstract: Techniques and mechanisms for providing socket connection to a substrate. In an embodiment, a socket device includes a first socket body portion that is to provide for signal exchanges as part of a socket connector including the first socket body portion and a second socket body portion. The first socket body portion and the second socket body portion comprise respective zones, wherein, of the two zones, only one such zone has a first electro-mechanical characteristic. The first electro-mechanical characteristic is selected from the group consisting of an interconnect dimension, an interconnect material, an interconnect structure, a socket body material, and a shielding structure. In another embodiment, modular socket sub-assemblies each comprise a respective one of the first zone and the second zone.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Anne M. SEPIC, Zhen ZHOU, Evan M. FLEDELL
  • Patent number: 9391447
    Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Evan M. Fledell, Paul B. Fischer, Roy E. Swart, Timothy J. Maloney, Jack D. Pippin
  • Patent number: 9128121
    Abstract: A mechanism is described for facilitating a dynamic electro-mechanical interconnect capable of being employed in a test system according to one embodiment. A method of embodiments of the invention may include separating, via a cavity, a first conductor of an interconnect from a second conductor of the interconnect, and isolating, via the cavity serving as a buffer, a first electrical path provided through the first conductor from a second electrical path provided through the second conductor.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Evan M. Fledell, Joe F. Walczyk, Dinia P. Kitendaugh
  • Publication number: 20140091824
    Abstract: A mechanism is described for facilitating a dynamic electro-mechanical interconnect capable of being employed in a test system according to one embodiment. A method of embodiments of the invention may include separating, via a cavity, a first conductor of an interconnect from a second conductor of the interconnect, and isolating, via the cavity serving as a buffer, a first electrical path provided through the first conductor from a second electrical path provided through the second conductor.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Evan M. Fledell, Joe F. Walczyk, Dinia P. Kitendaugh
  • Publication number: 20140029150
    Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.
    Type: Application
    Filed: March 6, 2012
    Publication date: January 30, 2014
    Inventors: Evan M. Fledell, Paul B. Fischer, Roy E. Swart, Timothy J. Maloney, Jack D. Pippin