Abstract: The various implementations described herein include a video camera assembly that includes: (1) a housing; (2) an image sensor positioned within the housing and having a field of view corresponding to a scene in the smart home environment; and (3) a concave-shaped front face positioned in front of the image sensor such that light from the scene passes through the front face prior to entering the image sensor; where the front face includes: (a) an inner section corresponding to the image sensor; and (b) an outer section between the housing and the inner section, the outer section having a concave shape that extends from an outer periphery of the outer section to an inner periphery of the outer section; and where the concave shape extends around an entirety of the outer periphery.

Abstract: The various implementations described herein include a video camera assembly that includes: (1) a housing; (2) an image sensor positioned within the housing and having a field of view corresponding to a scene in the smart home environment; and (3) a concave-shaped front face positioned in front of the image sensor such that light from the scene passes through the front face prior to entering the image sensor; where the front face includes: (a) an inner section corresponding to the image sensor; and (b) an outer section between the housing and the inner section, the outer section having a concave shape that extends from an outer periphery of the outer section to an inner periphery of the outer section; and where the concave shape extends around an entirety of the outer periphery.

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.

Abstract: Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.

Abstract: Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.

Abstract: This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

Abstract: A method includes determining initial load distribution data for a cargo area in an aircraft based on an estimated total weight of unloaded items. The cargo area includes a plurality of zones. The initial load distribution data includes a recommended weight for each of the zones and an estimated center of gravity (CG) for the aircraft as loaded with the items. The method includes displaying the initial load distribution data, acquiring a first weight value for a first set of items, and determining that the first set of items has been loaded into a first zone. The method includes determining updated load distribution data based on the first weight value and the location of the first zone in the aircraft. The updated load distribution data includes an updated recommended weight for each of the zones and an updated CG. The method includes displaying the updated load distribution data.

Abstract: In some examples, a time-based equalizer can be configured to receive an input signal from a channel. The input signal can be distorted by previously received input signals transmitted over the channel. The time-based equalizer can be configured to compensate for distortions in the input signal caused by at least one previously received input signal to provide an ISI compensated input signal. The time-based equalizer can be configured to compensate for the distortions by edge time shifting respective edges of the input signal in time over a time interval for detecting the input signal to new edge time locations based on a feedback signal and edge movement signals. The feedback signal can be generated based on at least one previously received input signal.

Abstract: While jobs with confidentiality are in principle kept from showing on a job list, display of the jobs with confidentiality is enabled with a simple operation. In an image forming apparatus, a display control section allows a display section to display a job list showing a plurality of executed jobs, wherein among the jobs, one job containing a predetermined word or character string representing confidentiality is excluded from the job list. When a predetermined keyword is input through a touch panel, the display control section allows the display section to display a confidential job containing the keyword.

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Abstract: While jobs with confidentiality are in principle kept from showing on a job list, display of the jobs with confidentiality is enabled with a simple operation. In an image forming apparatus, a display control section allows a display section to display a job list showing a plurality of executed jobs, wherein among the jobs, one job containing a predetermined word or character string representing confidentiality is excluded from the job list. When a predetermined keyword is input through a touch panel, the display control section allows the display section to display a confidential job containing the keyword.

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.

Abstract: In an example implementation according to aspects of the present disclosure, a method may include receiving, on a touch sensitive mat of a computing system, a touch input associated with a first event type. The method further includes determining whether to transform the touch input associated with the first event type to a different event type, and sending, to an application, the touch input associated with an event type based according to the determination.

Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

Abstract: In an example implementation according to aspects of the present disclosure, a method may include receiving, on a touch sensitive mat of a computing system, a touch input associated with a first event type. The method further includes determining whether to transform the touch input associated with the first event type to a different event type, and sending, to an application, the touch input associated with an event type based according to the determination.

Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.

Abstract: In an example implementation according to aspects of the present disclosure, a method may include receiving, on a touch sensitive mat of a computing system, a touch input associated with a first event type. The method further includes determining whether to transform the touch input associated with the first event type to a different event type, and sending, to an application, the touch input associated with an event type based according to the determination.

Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Abstract: Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.