Patents by Inventor Eve Marie Martin

Eve Marie Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6352894
    Abstract: A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: March 5, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Bernd Goebel, Wolfgang Roesner, Franz Hofmann, Emmerich Bertagnolli, Eve Marie Martin
  • Patent number: 6097049
    Abstract: A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the storage capacitor and the bit line are arranged substantially above a substrate, the bit line can be manufactured of materials having high electrical conductivity, and materials having a high dielectric constant can be utilized for the storage capacitor. At least the first source/drain zone and a channel zone are parts of a projection-like semiconductor structure that is laterally limited by at least two sidewalls. A respective word line can be arranged at the two sidewalls. An element that prevents the drive of the selection transistor by this word line is arranged between the channel zone and one of the word lines.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: August 1, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Bernd Goebel, Eve Marie Martin, Emmerich Bertagnolli
  • Patent number: 6044009
    Abstract: A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F.sup.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: March 28, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Bernd Goebel, Wolfgang Roesner, Franz Hofmann, Emmerich Bertagnolli, Eve Marie Martin