Patents by Inventor Everardo Torres Flores

Everardo Torres Flores has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnection for memory electrodes
    Patent number: 11715500
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20220084560
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 17, 2022
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • Interconnection for memory electrodes
    Patent number: 11139002
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20210280242
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • Memory device architecture
    Patent number: 11043267
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20200258552
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 13, 2020
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20200152263
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 14, 2020
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • Interconnection for memory electrodes
    Patent number: 10600452
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Memory device architecture
    Patent number: 10504589
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20190013068
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20190013052
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 10, 2019
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20190013069
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • Memory device architecture
    Patent number: 10141051
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 27, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • Interconnection for memory electrodes
    Patent number: 10056120
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 21, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20170358348
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 14, 2017
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20170352387
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 7, 2017
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • Interconnection for memory electrodes
    Patent number: 9767860
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 19, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Memory device architecture
    Patent number: 9734900
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • Connections for memory electrode lines
    Patent number: 9613902
    Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 4, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fabio Pellizzer, Everardo Torres Flores, Hernan A. Castro
  • CONNECTIONS FOR MEMORY ELECTRODE LINES
    Publication number: 20170033042
    Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 2, 2017
    Inventors: Fabio Pellizzer, Everardo Torres Flores, Hernan A. Castro