Patents by Inventor Everett A. McTeer

Everett A. McTeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12170250
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: December 17, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20240407160
    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A McTeer
  • Patent number: 12114492
    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
  • Publication number: 20240290722
    Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Application
    Filed: May 1, 2024
    Publication date: August 29, 2024
    Inventors: Jordan D. Greenlee, Lifang Xu, Rita J. Klein, Xiao Li, Everett A. McTeer
  • Patent number: 12034057
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: July 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John Mark Meldrim
  • Patent number: 12002759
    Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: June 4, 2024
    Inventors: Jordan D. Greenlee, Lifang Xu, Rita J. Klein, Xiao Li, Everett A. McTeer
  • Patent number: 11990528
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: May 21, 2024
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Publication number: 20240153877
    Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins, Rita J. Klein, Everett A. McTeer, Lifang Xu, Daniel Billingsley, Collin Howder
  • Patent number: 11894305
    Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 6, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins, Rita J. Klein, Everett A. McTeer, Lifang Xu, Daniel Billingsley, Collin Howder
  • Publication number: 20230395149
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 7, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, David Ross Economy, John D. Hopkins, Nancy M. Lomeli, Jiewei Chen, Rita J. Klein, Everett A. McTeer, Aaron P. Thurber
  • Publication number: 20230397424
    Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 7, 2023
    Inventors: Jordan D. Greenlee, Everett A. McTeer, Rita J. Klein, John D. Hopkins, Nancy M. Lomeli, Xiao Li, Christopher R. Ritchie, Alyssa N. Scarbrough, Jiewei Chen, Sijia Yu, Naiming Liu
  • Publication number: 20230387229
    Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Everett A. McTeer, Farrell M. Good, John M. Meldrim, Jordan D. Greenlee, Justin D. Shepherdson, Naiming Liu, Yifen Liu
  • Publication number: 20230389313
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 30, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Jiewei Chen, John D. Hopkins, Everett A. McTeer
  • Patent number: 11742282
    Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John D. Hopkins, Shuangqiang Luo, Song Kai Tan, Jing Wai Fong, Anurag Jindal, Chieh Hsien Quek
  • Patent number: 11705500
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Patent number: 11672191
    Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun J. Hu, Everett A. McTeer
  • Publication number: 20230154856
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20230121315
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Applicant: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Patent number: 11594495
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20230016742
    Abstract: Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoOxNy, where each of “x” and “y” is from 0 to 4.0; and (b): MoMz, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, Yongjun Jeff Hu, Rita J. Klein, Everett A. McTeer