Patents by Inventor Everett Allen McTeer
Everett Allen McTeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10325653Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.Type: GrantFiled: December 28, 2017Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
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Publication number: 20190140023Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Publication number: 20190097017Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20190088867Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall.Type: ApplicationFiled: January 29, 2018Publication date: March 21, 2019Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Patent number: 10224479Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: GrantFiled: January 29, 2018Date of Patent: March 5, 2019Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Patent number: 10177198Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: GrantFiled: June 5, 2017Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Patent number: 10164044Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: GrantFiled: April 16, 2015Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Patent number: 10079340Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: GrantFiled: April 4, 2016Date of Patent: September 18, 2018Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Publication number: 20180166629Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall.Type: ApplicationFiled: January 29, 2018Publication date: June 14, 2018Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Publication number: 20180144795Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.Type: ApplicationFiled: December 28, 2017Publication date: May 24, 2018Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
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Publication number: 20170358629Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: ApplicationFiled: June 5, 2017Publication date: December 14, 2017Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Patent number: 9673256Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: GrantFiled: March 7, 2016Date of Patent: June 6, 2017Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Publication number: 20170117449Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Patent number: 9608185Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: GrantFiled: April 25, 2014Date of Patent: March 28, 2017Assignee: Micron TechnologyInventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Publication number: 20160308018Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: ApplicationFiled: April 16, 2015Publication date: October 20, 2016Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20160218282Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Publication number: 20160204205Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.Type: ApplicationFiled: January 6, 2016Publication date: July 14, 2016Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
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Publication number: 20160190209Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Patent number: 9306159Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: GrantFiled: April 30, 2014Date of Patent: April 5, 2016Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Publication number: 20160093688Abstract: A multilayer source provides charge carriers to a multitier channel connector. The source includes a metal silicide layer on a substrate and a metal nitride layer between the metal silicide layer and the channel. The metal silicide and the metal nitride are processed without an intervening oxide layer between them. In one embodiment, the source further includes a silicon layer between the metal nitride layer and the channel. The silicon layer can also be processed without an intervening oxide layer. Thus, the source does not have an intervening oxide layer from the substrate to the channel.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer