Patents by Inventor Everett Basham

Everett Basham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7412923
    Abstract: A stencil device ensures that solder paste is accurately applied to a printed circuit board to create a substantially zero signal degradation solder bridge electrical connection. The printed circuit board is defined by a dielectric structure core having a first surface which further includes a first conducting pad having an edge and a second conducting edge having an edge separated from and adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. The stencil device includes a stencil plate member defining a first opening sized to substantially correspond to the first conducting pad, a second opening sized to substantially correspond to the second conducting pad, and a third opening. The third opening links the first opening to the second opening at a size to correspond to a partial portion of the surface area of the first surface between the edges of the first and second conducting pads.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: August 19, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Patent number: 7140531
    Abstract: A method of fabricating a substantially zero signal degradation electrical connection on a printed circuit board includes providing a printed circuit board defined by a dielectric structure core. The dielectric structure core has a first surface, which includes a first connecting pad having an edge and a second connecting pad having an edge separated from an adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. A solder paste is applied on the first and second conducting pads and on the first surface of the dielectric structure core. The solder paste at least partially covers the surface area of the first surface between the edges of the first and second conducting pads, thereby forming a substantially zero signal degradation electrical connection between the first and second conducting pads.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Publication number: 20050044702
    Abstract: A method of fabricating a substantially zero signal degradation electrical connection on a printed circuit board includes providing a printed circuit board defined by a dielectric structure core. The dielectric structure core has a first surface, which includes a first connecting pad having an edge and a second connecting pad having an edge separated from an adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. A solder paste is applied on the first and second conducting pads and on the first surface of the dielectric structure core. The solder paste at least partially covers the surface area of the first surface between the edges of the first and second conducting pads, thereby forming a substantially zero signal degradation electrical connection between the first and second conducting pads.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 3, 2005
    Inventors: Ian Shaeffer, Everett Basham, Christopher Price
  • Publication number: 20040041001
    Abstract: A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 4, 2004
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Patent number: 6664482
    Abstract: A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 16, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
  • Patent number: 6571357
    Abstract: The application discloses a system and method for providing a compact and high speed mechanism for emulating an ASIC or other chip operating within a large computing system environment for diagnostic purposes. A two step process is disclosed for generating data patterns for fully exercising a chip and to then transmit these data patterns at a high frequency to a system under test. In phase one, a pattern generator preferably transmits test pattern data at a first frequency to a memory storage device. In phase two, the memory storage device is enabled to transmit the stored test pattern data at a high frequency to a system under test. Buffering the test pattern data in this manner enables the inventive system to bypass the data transmission speed limitation of the pattern generator while still employing the test patterns created by the pattern generator and to thereby test the system under test under high speed operating conditions.
    Type: Grant
    Filed: April 29, 2000
    Date of Patent: May 27, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew A. Martin, Everett Basham, Christopher D. Price
  • Publication number: 20030014728
    Abstract: A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.
    Type: Application
    Filed: September 13, 2002
    Publication date: January 16, 2003
    Inventors: Ian P. Shaeffer, Everett Basham
  • Patent number: 6460170
    Abstract: A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.
    Type: Grant
    Filed: April 29, 2000
    Date of Patent: October 1, 2002
    Assignee: Hewlett Packard Company
    Inventors: Ian P. Shaeffer, Everett Basham