Patents by Inventor Everett Lee

Everett Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Direct alignment scheme between multiple lithography layers
    Patent number: 7547597
    Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Derchang Kau, Khaled Hasnat, Everett Lee
  • Simultaneous selective polymer deposition and etch pitch doubling for sub 50nm line/space patterning
    Publication number: 20070228002
    Abstract: First radicals and second radicals are simultaneous deposited into a space defined by two adjacent lines of photoresists and an underlying layer. A portion of the first radicals and the second radicals combine to form a polymer layer on the layer in the center of the space, and substantially simultaneously, another portion of thee first radicals remove the underlying layer near the base of the photoresists. The first radicals may be fluorine-rich and the second radicals may be carbon-rich.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Qiquan Geng, Jeff Xu, Everett Lee, Michael Ru, Hsu-en Yang, Chung Hui
  • Direct alignment scheme between multiple lithography layers
    Publication number: 20060267224
    Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
    Type: Application
    Filed: August 7, 2006
    Publication date: November 30, 2006
    Inventors: Derchang Kau, Khaled Hasnat, Everett Lee
  • Direct alignment scheme between multiple lithography layers
    Patent number: 7087943
    Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Derchang Kau, Khaled Hasnat, Everett Lee
  • Light source for photolithography
    Publication number: 20050225740
    Abstract: A hybrid light source for photolithography is disclosed. According to an embodiment of the invention, a light source comprises, a head, a first set of poles coupled to the head, the first set of poles are located approximately at an outer edge of the head, and a second set of poles coupled to the head located between the outer edge and a center of the head. According to a further embodiment of the invention, the poles are adjustable to change the characteristics of the light source.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Sushil Padlyar, Hsuen Yang, Everett Lee
  • Contactless flash memory array
    Publication number: 20050139935
    Abstract: A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulating layer is removed to form a one-dimensional slot and to provide access to the active regions. A bit line is then formed in the slot in contact with the active regions.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 30, 2005
    Inventor: Everett Lee
  • Direct alignment scheme between multiple lithography layers
    Publication number: 20040224262
    Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 11, 2004
    Applicant: Intel Corporation
    Inventors: Derchang Kau, Khaled Hasnat, Everett Lee
  • Method for improved line patterning by chemical diffusion
    Publication number: 20030003408
    Abstract: A method and articles of manufacture created from this method wherein a portion of a layer of photoresist material are irradiated to cause the creation of a chemical within that portion, and then the passage of time and/or the application of heat is used to cause the chemical to propagate to another portion of the layer of photoresist material.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Everett Lee, Susan Kao
  • Method for improved line patterning by chemical diffusion
    Publication number: 20030003403
    Abstract: A method and articles of manufacture created from this method wherein a portion of a layer of photoresist material are irradiated to cause the creation of a chemical within that portion, and then the passage of time and/or the application of heat is used to cause the chemical to propagate to another portion of the layer of photoresist material.
    Type: Application
    Filed: September 7, 2001
    Publication date: January 2, 2003
    Inventors: Everett Lee, Susan Kao