Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal.

Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.

Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal.

Abstract: An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.

Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection m

Abstract: An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.

Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Abstract: An apparatus comprising: a plurality of processors, a data bus, shared by the plurality of processors, and configured to at least receive data processed by each of the plurality of processors when performing predetermined tasks, the plurality of processors and data bus comprising at least part of a hardware based real-time computing system; a controller configured to provide for control of a maximum data rate at which data is provided to the data bus for transmission thereover by at least one of the plurality of processors in performing at least one of the predetermined tasks, wherein the controller is configured to provide for a maximum data rate at least comprising an impeded rate for the at least one predetermined tasks and an unimpeded rate wherein the impeded rate is less than the unimpeded rate.

Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection m

Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.

Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.

Abstract: A testable processor system (10,20) comprises a plurality of modules (11, 12, . . . In). Each module (11) comprises a processor unit (110) and a debug controller (111). The debug controllers are coupled to a common test access point controller (TAP-controller 20), and have a test data input (Tin), a test data output (Tout) and at least one test register (112, 113). The test data inputs and outputs of the debug controllers (111, 121, 131, . . . , InI) are arranged in a scan chain having an input for receiving test input data (TDI) from the TAP-controller and an output for providing test output data (TDO) to the TAP-controller. At least one debug controller (111) has a selection facility (115) to select whether data in the scanchain is either shifted through the at least one test register (112) of that debug controller (111) or is immediately forwarded from the test data input (Tin) to the test data output (Tout) of that debug controller.

Abstract: Non-overlapping cache locations are reserved for each data stream. Therefore, stream information, which is unique to each stream, is used to index the cache memory. Here, this stream information is represented by the stream identification. In particular, a data processing system optimised for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources is provided. An unambiguous stream identification is associated to each of said data stream. Said data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks, wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for controlling said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (22). A remote write only structure (14a-d) couples outputs of respective groups of the digital signal processors (10) each to the multiplexed data input (16) of respective particular digital signal processor (10), the respective group for the particular digital signal processor (10) not including the particular digital signal processor (10). Thus, each processor (10) writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors (10) via memory, where it is received via an input that does not share resources with the output of the processor (10).

Abstract: The invention relates to task management in a data processing system, having a plurality of processing elements (CPU, ProcA, ProcB, ProcC). Therefore a data processing system is provided, comprising at least a first processing element (CPU, ProcA, ProcB, ProcC) and a second processing element (CPU, ProcA, ProcB, ProcC) for processing a stream of data objects (DS_Q, DS R, DS S, DST), the first processing element being arranged to pass data objects from the stream of data objects to the second processing element The first and the second processing element are arranged for parallel execution of an application comprising a set of tasks (TP, TA, TB1, TB2, TC), and the first and the second processing element are arranged to be responsive to the receipt of a unique identifier. In order to ensure integrity of data during reconfiguration of the application, the unique identifier is inserted into data stream and passed from one processing element to the other.

Abstract: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: A series (20) of original instructions for a single processor is translated into implementing instructions for executions distributed over a plurality of processors (12,16) of different type. The series (20) of original instructions is split into successive sections (22a-c,24a,b) assigned to respective ones of the processors (12,16). Operand transfer instructions are added to the sections (22a-c,24a,b) to support data dependencies between the sections (22a-c,24a,b). The assignment includes selecting a location of a boundary in the series of original instructions between successive ones of the sections (22a-c,24a,b) so as to substantially minimize an aggregate of the execution cost factors of the original instructions as implemented and including costs for the operand transfer instructions. Preferably, the locations of the boundaries are determined from a search among different boundaries positions.

Abstract: Transform based coders are frequently used in digital signal processing. The present invention relates to a method of communicating at least one block of data from a first functional element (3; 4; 7; 12; 14) within a transform based coder (1) or decoder (10) to a second functional element (4; 5; 7; 8; 14; 15) within the coder or decoder, where the block of data comprises a row-column structure of data coefficients. A significant communication workload occurs between individual elements of the coders and decoders.

Abstract: The invention is based on the idea to provide distributed task scheduling in a data processing system having multiple processors. Therefore, a data processing system comprising a first and at least one second processor for processing a stream of data objects, wherein said first processor passes data objects from a stream of data objects to the second processor, and a communication network and a memory is provided. Said second processors are multi-tasking processors, capable of interleaved processing of a first and second task, wherein said first and second tasks process a first and second stream of data objects, respectively. Said data processing system further comprises a task scheduling means for each of said second processors, wherein said task scheduling means is operatively arranged between said second processor and said communication network, and controls the task scheduling of said second processor.