Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.

Abstract: An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.

Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

Abstract: A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

Abstract: A cathode ray tube device in which two deflection yokes and two electron guns are used, but in which only one shadow mask is used. Image uniformity is obtained by creating a partial overlap of the two images created by the two yokes.

Abstract: A cathode ray tube device in which two deflection yokes and two electron guns are used, but in which only one shadow mask is used. Image uniformity is obtained by creating a partial overlap of the two images created by the two yokes.

Abstract: A cathode ray tube device in which two deflection yokes and two electron guns are used, but in which only one shadow mask is used. Image uniformity is obtained by creating a partial overlap of the two images created by the two yokes.

Abstract: In transconductance amplifier arrangements used in CATV systems, it is often desirable to set the value of the output impedance to a value equal to the system impedance that is often 75&OHgr;. prior art transconductance amplifiers often comprise an amplifier (6) with a current output using a feedback network (8) to set the gain value. An input of the feedback network (8) is coupled to the current output of the amplifier (6) and an output of the feedback network (8) is coupled to the input of the amplifier (6). In these prior art transconductance amplifier arrangements the output impedance decreases with increasing gain of the amplifier (6) used in the amplifier arrangement. This output impedance is normally very low (a few &OHgr; or lower). By adding a further output current (i/N) to the output of the feedback network, it is obtained that the current through the feedback network (8) becomes dependent on the output current (i) of the amplifier. This dependence results in an increased output impedance.

Abstract: A memory in an integrated circuit contains a current sense amplifier. The current sense amplifier contains a first and second input transistor with cross-coupled gates and drains, each transistor having a source coupled to a respective memory bit line. The current from the drains of the first and second input transistor is guided to source-drain channels of the first and second load transistor respectively. The drains of the first and second input transistor are coupled to a common node via source-gate links of the first and second load transistor respectively. The gate/source voltage drops of the first and second load transistor are arranged in a direction opposite to a direction of gate/source voltage drops of the first and second input transistor between the complementary bit lines and the common node.

Abstract: To prevent breakdown of an insulating layer located underneath a gate electrode, the gate electrode is connected to an external terminal via a high-ohmic resistor. The high-ohmic resistor may form part of a resistive network for biasing voltages for a plurality of gate electrodes. The resistive network may be realised partly on the insulating layer.

Abstract: A voltage-current converter includes a signal voltage source (2), a series resistor (4) and an electronic circuit with a first transconductance amplifier (12) and a second transconductance amplifier (22). The corresponding inputs (16, 20; 24, 26) of the transconductance amplifiers (12, 22) are connected to receive a voltage difference (V.sub.A) between a node (18) and a reference terminal (8). The output (14) of the first transconductance amplifier (12) is connected to an input terminal (6) to which the series resistor (4) is connected as well. The output (25) of the second transconductance amplifier (22) is connected to an output terminal (10). Due to feedback around the first transconductance amplifier (12) an input current (i.sub.1) can flow into the input terminal (6). The input current (i.sub.1) is amplified or copied by the second transconductance amplifier (22) and is available at an output terminal (10). The input current (i.sub.

Abstract: In a differential pair (P1, P2) actively loaded with a current mirror (N1, N2), a differential amplifier (A) drives the common terminal (Z) of the current mirror to force a zero voltage difference between the input terminal (X) and the output terminal (Y) of the current mirror. The voltage at the input terminal (X) is actively bootstrapped, via the differential amplifier (A), by the voltage of the output terminal (Y) with high precision. Thus a high voltage gain is obtained. A capacitor (CP) between the input terminal (X) and the control terminal (Z) compensates the local loop formed by the differential amplifier (A) and the input transistor (N1) of the current mirror, and forms a short circuit at high frequencies, thus reducing the active load of the differential pair to a conventional current mirror. For high frequencies the circuit has the same gain and phase properties as the standard non-bootstrapped approach and standard compensating techniques can be applied to the complete amplifier.

Abstract: A CMOS bias circuit capable of operating down to a supply voltage equal to the sum of the threshold voltage and the saturation voltage. It generates a threshold referenced bias voltage which is independent of the supply voltage. This bias voltage is equal to the gate source voltage of a transistor which supplies a current equal to the gate-source voltage of another transistor divided by the resistance of a feedback resistor. Via the feedback resistor, changes in the supply voltage cause counteracting changes in the gate-source voltages of the transistors, resulting in a bias voltage which is substantially constant with changing supply voltage.

Abstract: In the case of amplifier circuits realised in modern MOS technology, non-linear distortion occurs as a result of the high field strengths in the channel region due to the small dimensions. This distortion is eliminated and noise is reduced in that the amplifier circuit comprises a first series combination of first and second MOS transistors, and a second series combination identical with the first series combination and forming a long tailed pair circuit with the latter. The long tailed pair circuit includes an additional differential amplifier having its output connected to the gate electrode of a load transistor of the long tailed pair circuit by way of a voltage divider. The transistors in the long tailed pair circuit are mutually identical.

Abstract: A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).

Abstract: An integrated circuit includes a sense amplifier which has an equalizing effect on voltages on the inputs of the sense amplifier, in particular during readout of the sense amplifier. The sense amplifier includes a parallel connection of a first and second current branch, each current branch including a control transistor, the source of which is connected to a relevant input, and the gate of which is connected to the drain of the control transistor in the other current branch, and a load transistor, whose gate receives a selection signal being connected in each said current branch in series with the control transistor. During readout, the gate of the load transistor is driven so as to make the channel of the load transistor conductive.

Abstract: An integrated memory includes a sense amplifier which has a parallel connection of a first and a second current branch, each current branch including channels of a control transistor and a load transistor which are coupled via a junction point, the junction points in each current branch being cross-wise coupled to the gates of the load transistors in the other current branch, and the junction points constituting outputs of the sense amplifier. The control and load transistors are of the same conductivity type, with each load transistor being connected in a source-follower configuration with its associated control transistor. As a result, the control transistors will be operative in the saturation region at all times and can be driven to full output, so that an integrated memory incorporating the invention is faster.

Abstract: A buffer circuit for buffering an applied reference voltage at a low output impedance. The buffer circuit includes an input transistor which is coupled to an external reference voltage and to an external reference current, and a voltage-to-current converter for applying less or more current to an output terminal of the buffer circuit. This provides a substantially temperature-independent and stable buffer circuit which consumes very little quiescent current.