Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: There is disclosed in one example a computing system, including: a processor including one or more computing cores; a cache having n discrete cache banks of the same cache level; and a cache controller including n discrete cache buses to communicatively couple the cache controller to the cache, wherein the cache buses are of width b, and a cache access controller configured to: receive an access request for an object of size s, wherein s>b; divide the object into k chunks of size b or smaller; and transfer the object to or from the cache in one or more iterations, the iterations including transferring n chunks of size b or smaller in parallel via the cache buses.

Abstract: A method and apparatus are provided for classifying received network frames (206) by extracting frame header data (e.g., n-tuple) which is combined with a key insert value (e.g., embedded prefix value “OP01, OP02, . . . OP0OP1”) to generate a lookup key (216), where the key insert value is generated by decoding a key composition rule (235) to extract a constant value (OP0) and a repeat value (OP1), and then replicating the constant value one or more times specified by the repeat value.

Abstract: In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. The method also includes preventing reallocation of a timer identifier (ID) associated with the timer to another timer after the expiration of the timer and until receipt of the timer release confirmation message at the timer management component.

Abstract: A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. A sufficiency of a temporal separation, between updating the data leaf and searching for the data leaf, to retrieve the data leaf is determined. Each search result is cleared when the temporal separation is insufficient. A new search is performed when the temporal separation is insufficient.

Abstract: A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

Abstract: Methods and systems are disclosed for non-intrusive debug processing of network frames. For certain embodiments, a frame parser processes frames from a network interface and generates frame metadata. A key generation engine processes each frame and its related metadata to generate a normal key and a debug key. The same key composition rule formats and key generation engine are used to generate the normal key and the debug key to provide non-intrusive debug processing. Frame classification logic compares the normal key to classification tables to determine a frame classification for the received frame. Separate debug comparison logic compares the debug key to debug reference data/masks to generate debug markers for the received frame. The frame classification and the debug markers for each frame are provided to frame marking logic, and a frame processing engine then processes the resulting marked/classified frames.

Abstract: Methods and systems are disclosed to embed valid-field (VF) bits into classification keys for network packet frames. The embedded VF bits allow for extracted data from existing fields associated with frame data to be distinguished from default data used for missing fields where this extracted data and default data has been included within a frame classification key generated for a network packet frame. In certain embodiments, a valid-field field extraction command (VF-FEC) causes a key generator to embed VF bits into a frame classification key, and the logic state of the VF bits are used to distinguish extracted data from default data. Further, the disclosed embodiments allow VF bits to be selectively cleared based upon a bit mask applied prior to embedding of the VF bits. Still further, users can define VF-FECs and other field extraction commands (FECs) for key generation through one or more programmable key composition rules.

Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.

Abstract: A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

Abstract: A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. A sufficiency of a temporal separation, between updating the data leaf and searching for the data leaf, to retrieve the data leaf is determined. Each search result is cleared when the temporal separation is insufficient. A new search is performed when the temporal separation is insufficient.

Abstract: In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. The method also includes preventing reallocation of a timer identifier (ID) associated with the timer to another timer after the expiration of the timer and until receipt of the timer release confirmation message at the timer management component.

Abstract: A method and apparatus are provided for classifying received network frames (106) by using a key composition rule (134) having a header portion (NF) and multiple variable length key extract commands in a coded order sequence to sequentially generate multiple data fields (FIELD 1-FIELD n) using operands contained in the key extract commands to generate a lookup key (116) by combining multiple data fields in the same coded order sequence as the key extract commands.

Abstract: Methods and systems are disclosed to embed valid-field (VF) bits into classification keys for network packet frames. The embedded VF bits allow for extracted data from existing fields associated with frame data to be distinguished from default data used for missing fields where this extracted data and default data has been included within a frame classification key generated for a network packet frame. In certain embodiments, a valid-field field extraction command (VF-FEC) causes a key generator to embed VF bits into a frame classification key, and the logic state of the VF bits are used to distinguish extracted data from default data. Further, the disclosed embodiments allow VF bits to be selectively cleared based upon a bit mask applied prior to embedding of the VF bits. Still further, users can define VF-FECs and other field extraction commands (FECs) for key generation through one or more programmable key composition rules.

Abstract: A method and apparatus are provided for classifying received network frames (234) by extracting frame header data (e.g., n-tuple) which is combined with a key insert value (e.g., embedded prefix value “OP01, OP02, . . . OP0OP1”) to generate a lookup key (217), where the key insert value is generated by decoding a key composition rule (212) to extract a constant value (OP0) and a repeat value (OP1), and then replicating the constant value one or more times specified by the repeat value.

Abstract: Methods and systems are disclosed for non-intrusive debug processing of network frames. For certain embodiments, a frame parser processes frames from a network interface and generates frame metadata. A key generation engine processes each frame and its related metadata to generate a normal key and a debug key. The same key composition rule formats and key generation engine are used to generate the normal key and the debug key to provide non-intrusive debug processing. Frame classification logic compares the normal key to classification tables to determine a frame classification for the received frame. Separate debug comparison logic compares the debug key to debug reference data/masks to generate debug markers for the received frame. The frame classification and the debug markers for each frame are provided to frame marking logic, and a frame processing engine then processes the resulting marked/classified frames.

Abstract: A data management system comprises a trie data structure. The trie data structure comprises a plurality of interconnected nodes wherein at least a portion of said plurality of interconnected nodes is configured as parent nodes and child nodes, wherein at least one child node comprises an identifier of its parent node.

Abstract: A device and a method for performing bitwise manipulation is provided. Multiple bitwise logic circuits are coupled to an instruction decoder, a register array and a rotator. Each bitwise logic circuit includes input multiplexers connected to an output multiplexer. The instruction decoder receives a bit manipulation instruction and sends to each corresponding input multiplexer a control signal based on a type of the instruction. Each input multiplexer of each bitwise logic circuit receives a control signal, a constant signal that has a value that is indifferent to the value of the mask, and a mask affected signal that has a value that is responsive to a value of an associated mask bit. Each input multiplexer selects between the constant signal and the mask affected signal based on the control signal, and outputs a selected signal.

Abstract: A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.