Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.

Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.

Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

Abstract: A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.

Abstract: A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. A processor may include load buffer entries having predictor table entries associated therewith, including saturation counters to record history of previous conflicts between loads and stores corresponding to the same target address. A watchdog unit may disable memory disambiguation (MD) if the MD causes too high a misprediction rate for load operation and store operation conflicts. In one embodiment, the MD is disabled if a flush counter value reaches a threshold.

Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. In an embodiment, a load operation may be predicted to not conflict with older pending store operations if a saturation counter corresponding to the load operation is below a threshold value and a maximum rate of mispredictions has not occurred. Other embodiments are also disclosed.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: A method and apparatus for executing low power validations for high confidence predictions. More particularly, the present invention pertains to using confidence levels of speculative executions to decrease power consumption of a processor without affecting its performance. Non-critical instructions, or those instructions whose prediction, rather than verification, lie on the critical path, can thus be optimized to consume less power.

Abstract: A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a memory. The method includes processing a first plurality of memory cells and a second plurality of memory cells in the memory. The method determines if a memory block is a last recently accessed memory block. The method determines whether a memory block accessed is a hit or a miss. The method accesses a lower memory level if the memory block accessed is a miss. Also, processing the second plurality of memory cells for an exact block if the block accessed is a hit but not the last recently accessed memory block. And, providing the memory block for additional access if the memory block accessed is a hit and is a last recently accessed memory block.

Abstract: A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a memory. The method includes processing a first plurality of memory cells and a second plurality of memory cells in the memory. The method determines if a memory block is a last recently accessed memory block. The method determines whether a memory block accessed is a hit or a miss. The method accesses a lower memory level if the memory block accessed is a miss. Also, processing the second plurality of memory cells for an exact block if the block accessed is a hit but not the last recently accessed memory block. And, providing the memory block for additional access if the memory block accessed is a hit and is a last recently accessed memory block.