Abstract: In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for controlling a protocol analysis device when a code execution breakpoint is encountered. The method includes displaying computer code in a user interface of a software development program. The computer code includes a breakpoint. The computing system receives user input to cause a first hardware device to execute the computer code. The computing system instructs the first hardware device to execute the computer code. The computing system instructs a protocol analysis device that is in communication with the computing system to begin recording data that is transmitted between the first hardware device and a second hardware device. The computing system determines that execution of the computer code has reached the breakpoint and as a result instructs the protocol analysis device to start or stop recording the data.

Abstract: In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for controlling a protocol analysis device when a code execution breakpoint is encountered. The method includes displaying computer code in a user interface of a software development program. The computer code includes a breakpoint. The computing system receives user input to cause a first hardware device to execute the computer code. The computing system instructs the first hardware device to execute the computer code. The computing system instructs a protocol analysis device that is in communication with the computing system to begin recording data that is transmitted between the first hardware device and a second hardware device. The computing system determines that execution of the computer code has reached the breakpoint and as a result instructs the protocol analysis device to start or stop recording the data.

Abstract: The invention describes a semi-automated method and system for Field Programmable Gate Array (FPGA) timing closure. The method is used to achieve timing closure by storing all previous results of design synthesis, place & route, tool options, and area constraints in a database, applying a set of analysis algorithms on the entire build history, and applying a decision engine to determine set of synthesis and place & route tool options and area constraints for the next build iteration. The aim of the inventive method is to eliminate most of the manual steps during design timing closure. The inventive method further makes the process faster, requiring fewer build iterations, and more robust to small design changes that can affect timing results. The desired outcome is achieved by making decisions based on the analysis of all the previous build results.

Abstract: A method for performing wireless analyzer spatial position optimization for a network having a particular network topology. The method comprises the steps of recording one or more reference network topology measurements to perform an initial parameter calibration, estimating a plurality of possible relative positions for the particular network topology, and calculating a link estimator function for each link between a plurality of the possible relative positions. Recording quality for each received packet is calculated at each of the plurality of possible relative positions over each of the links so that a position indicative of an optimal position is determined.

Abstract: A method and apparatus for synchronizing with a network without connecting to the network by shadowing a slave device while a master device connects the slave device to the network. The master device maintains a system clock time. The master and slave devices exchange communication traffic during time slots on channels in a channel hopping sequence derived from the system clock time. The method and apparatus obtain a slave clock time in an inquiry response packet from a slave device when the master and slave devices are not connected in the network and then use the slave clock time for shadowing the slave device for receiving a master page frequency hop synchronization (FHS) packet having the system clock time.