Abstract: Power efficient performance may be implemented in a hardware accelerator (e.g., a neural processor) comprising hybrid or analog multiply and accumulate (MAC) processing elements (PEs). For example, power consumption may be reduced in neural networks with a rectified linear unit (ReLU) activation layer. A hybrid or analog MAC circuit may be configured with a look-ahead sign detector to dynamically stop computations prior to completion, for example, based on detection of a negative value, which a ReLU activation layer may (e.g., subsequently) convert to zero. The sign of a value may be indicated by a most significant bit (MSB). A controller may provide power and/or clock cycles to an analog to digital converter (ADC) to determine a sign of a value being computed. The sign may be used to selectively complete computations for positive values and selectively terminate computations for negative values, thereby reducing power consumption of the MAC circuit.

Abstract: Systems, methods, and devices are described for generating multi-tone waveforms. A count signal having a count value is generated. A plurality of step values and a plurality of phase values are received. For each increment of the count value, an index value corresponding to each step value of the plurality of step values is calculated based on the step value, the count value, and a respective phase value of the plurality of phase values. A tone point value corresponding to each calculated index value is determined to generate a plurality of tone point values for each increment of the count value. The determined tone point values are summed to generate a corresponding waveform point for each increment of the count value. A waveform is generated as a sequence of generated waveform points.

Abstract: A multimedia sink apparatus and method thereof, for fast switching between a plurality of source multimedia devices. The apparatus comprises a plurality of input ports, each of the plurality of input ports is connected to a source multimedia device through a high bandwidth multimedia interface; and a plurality of high-bandwidth digital content protection (HDCP) receivers, each of the plurality of the HDCP receivers is connected to an input port, wherein each of the plurality of the HDCP receivers is adapted to perform a first authentication part of a HDCP authentication process, and upon reception of an indication that a respective source device connected to the respective input was selected, to perform a third authentication part of the HDCP authentication process.