Patents by Inventor Evgueni Goldberg

Evgueni Goldberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7853903
    Abstract: An improved method and mechanism for verification of an electrical circuit design is provided. The method and system simultaneously provides the coverage advantage of formal verification with the scaling efficiencies of simulation. In one approach, the method and system generates an intelligent set of test vectors off a resolution proof. The intelligent set of test vectors can be used to simulate the circuit design for complete coverage without having to test the entire set of possible variable assignments for the CNF formula corresponding to the circuit design.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Evgueni Goldberg, Felice Balarin
  • Patent number: 7610570
    Abstract: An improved method and mechanism for designing and verifying an electrical circuit design is provided using an improved SAT-solver which uses complete assignments and systematic local search to provides improved performance. In one approach, the sat-solver maintains a complete assignment that is changed one variable at a time. A variable is fixed within the falsified set of clauses.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 27, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Evgueni Goldberg
  • Patent number: 7600211
    Abstract: A method of synthesis of a second circuit (N2) that is toggle equivalent to a first circuit (N1), comprising building up N2 in topological order, starting from the input side of N2, by producing a sequence of subcircuit designs N2(1) through N2(k), such that output toggling of circuit N1 implies output toggling of subcircuit N2(1) for every i=1, . . , k; and output toggling of N2(j) strictly implies output toggling of N2(i) if i<j.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: October 6, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Evgueni Goldberg, Kanupriya Gulati
  • Patent number: 7356519
    Abstract: A method and system for solving satisfiability problems is disclosed. In one embodiment, clauses in a satisfiability problem are organized as a chronologically ordered stack. In another embodiment, the activity of each variable in the satisfiability problem is monitored. An activity counter is maintained for each variable and is incremented each time the variable appears in a clause used in generating a conflict clause. In an embodiment, a branching variable is selected from among the variables in the top clause of the stack when the top clause is a conflict clause. In a further embodiment, one or more conflict clauses in the stack are removed when the search tree is abandoned. In a still further embodiment, the value assigned to a branching variable is selected for purposes of having a uniform distribution of positive and negative literals.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: April 8, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Evgueni Goldberg, Yakov Novikov