Patents by Inventor Evgueniy Stefanov

Evgueniy Stefanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9559198
    Abstract: A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: January 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Evgueniy Stefanov, Edouard de Fresart, Philippe Dupuy
  • Patent number: 9472662
    Abstract: A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 18, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Edouard Denis De Fresart, Moaniss Zitouni
  • Publication number: 20160247916
    Abstract: A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.
    Type: Application
    Filed: September 30, 2015
    Publication date: August 25, 2016
    Inventors: EVGUENIY STEFANOV, EDOUARD DENIS DE FRESART, MOANISS ZITOUNI
  • Publication number: 20160197176
    Abstract: A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: July 7, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Evgueniy Stefanov, Edouard de Fresart, Philippe Dupuy
  • Patent number: 8779465
    Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: July 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean-Michel Reynes, Philippe Lance, Evgueniy Stefanov, Yann Weber
  • Patent number: 8217448
    Abstract: A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: July 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Alain Deram, Jean-Michel Reynes
  • Patent number: 8188539
    Abstract: A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: May 29, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean-Michel Reynes, Isabelle Majoral, Jean-Pierre Pujo, Evgueniy Stefanov
  • Patent number: 7955929
    Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 7, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Ivana Deram, Jean-Michel Reynes
  • Publication number: 20100155828
    Abstract: A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region.
    Type: Application
    Filed: August 10, 2005
    Publication date: June 24, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jean-Michel Reynes, Isabelle Majoral, Jean-Pierre Pujo, Evgueniy Stefanov
  • Publication number: 20100109078
    Abstract: A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer.
    Type: Application
    Filed: January 4, 2007
    Publication date: May 6, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Alain Deram, Jean-Michel Reynes
  • Publication number: 20100001344
    Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.
    Type: Application
    Filed: January 10, 2007
    Publication date: January 7, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stefanov, Ivana Deram, Jean-Michel Reynes
  • Patent number: 6953980
    Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: October 11, 2005
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Rene Escoffier, Evgueniy Stefanov, Jeffrey Pearse, Francine Y. Robb, Peter J. Zdebel
  • Publication number: 20050006706
    Abstract: In one embodiment, an SCR device (41) includes a p+ wafer (417), a p? layer (416), an n+ buried layer (413) and an n? layer (414). P? wells (411,421) are formed in the n? layer (414). N+ regions (412,422) and p+ regions (415,425) are formed in the p? wells (411,421). A first ohmic contact (431) couples one n+ regions (422) to one p+ region (425). A second ohmic contact (433) couples another n+ region (412) to another p+ region (415) to provide physically and electrically symmetrical low-voltage p-n-p-n silicon controlled rectifiers. A deep isolation trench (419) surrounding the SCR device (41) and dopant concentration profiles provide a low capacitance SCR design for protecting high frequency integrated circuits from electrostatic discharges.
    Type: Application
    Filed: July 9, 2003
    Publication date: January 13, 2005
    Inventors: Evgueniy Stefanov, Rene Escoffier
  • Patent number: 6773997
    Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: August 10, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Mohamed Imam, Joe Fulton, Zia Hossain, Masami Tanaka, Taku Yamamoto, Yoshio Enosawa, Katsuya Yamazaki, Evgueniy Stefanov
  • Patent number: 6773977
    Abstract: The present invention relates to a method of forming a diode (2) for integration with a semiconductor device comprising the steps of providing a layer (4) of semiconductor material, forming a dielectric layer (6) over the layer of semiconductor material, introducing a first conductivity type dopant into the dielectric layer (6), forming a semi-conductive layer (8) over the dielectric layer (6), introducing a second conductivity type dopant into a first region (12) of the semi-conductive layer and re-distributing the first conductivity type dopant from the dielectric layer (6) into the semi-conductive layer (8) so as to form a second region (18) of the first conductivity type dopant in the semi-conductive layer (8), the second region (18) being adjacent the first region (12) so as to provide a P/N junction of the diode (2).
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: August 10, 2004
    Assignees: Freescale Semiconductor, Inc., Semiconductor Components Industries, LLC
    Inventors: Jean-Michel Reynes, Ivana Deram, Evgueniy Stefanov
  • Publication number: 20030228848
    Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 11, 2003
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Rene Escoffier, Evgueniy Stefanov, Jeffrey Pearse, Francine Y. Robb, Peter J. Zdebel