Abstract: Cameras are located within the display area of a display. In-display cameras allow for thinner display bezels. In-display cameras allow for the creation of ultra-high resolution images. The ability to capture an object from multiple perspectives allows for holographic image recording and playback. Multiple views of an image can be captured with varying depths of focus, allowing an image's depth of field to be adjusted during post processing. In-display cameras can also be used for user authentication, touch detection and three-dimensional gesture recognition. Thermal sensors located within the display area allow for control of the display temperature, improved control over system performance, and compensation for micro-LED degradation that can occur due to aging or increased temperature. Microlens assemblies located above pixels can adjust the viewing cone angle of the display or a portion of the display and microassemblies located under individual pixels or pixel arrays can adjust a viewing angle.

Abstract: A display comprising a display substrate comprising a front side; a plurality of pixels located on the front side of the display substrate, the plurality of pixels defining a display area; and an antenna array comprising a plurality of antennas located on the front side of the display substrate and within the display area.

Abstract: Cameras are located within the display area of a display. In-display cameras allow for thinner display bezels. In-display cameras allow for the creation of ultra-high resolution images. The ability to capture an object from multiple perspectives allows for holographic image recording and playback. Multiple views of an image can be captured with varying depths of focus, allowing an image's depth of field to be adjusted during post processing. In-display cameras can also be used for user authentication, touch detection and three-dimensional gesture recognition. Thermal sensors located within the display area allow for control of the display temperature, improved control over system performance, and compensation for micro-LED degradation that can occur due to aging or increased temperature. Microlens assemblies located above pixels can adjust the viewing cone angle of the display or a portion of the display and microassemblies located under individual pixels or pixel arrays can adjust a viewing angle.

Abstract: Cameras are located within the display area of a display. In-display cameras allow for thinner display bezels. In-display cameras allow for the creation of ultra-high resolution images. The ability to capture an object from multiple perspectives allows for holographic image recording and playback. Multiple views of an image can be captured with varying depths of focus, allowing an image's depth of field to be adjusted during post processing. In-display cameras can also be used for user authentication, touch detection and three-dimensional gesture recognition. Thermal sensors located within the display area allow for control of the display temperature, improved control over system performance, and compensation for micro-LED degradation that can occur due to aging or increased temperature. Microlens assemblies located above pixels can adjust the viewing cone angle of the display or a portion of the display and microassemblies located under individual pixels or pixel arrays can adjust a viewing angle.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example electronic device disclosed herein includes a microphone and a thermal management system having a fan. The electronic device includes a processor to detect ambient noise via the microphone, identify a sound of interest value associated with the ambient noise and identify a background noise value associated with the ambient noise. The processor to determines a signal-to-noise ratio based on the sound of interest value and the background noise value and compares the signal-to-noise ratio to a sensitivity threshold. In response to determining that the signal-to-noise ratio exceeds the sensitivity threshold, the processor operates the thermal management system with one or more restrictions.

Abstract: Cameras are located within the display area of a display. In-display cameras allow for thinner display bezels. In-display cameras allow for the creation of ultra-high resolution images. The ability to capture an object from multiple perspectives allows for holographic image recording and playback. Multiple views of an image can be captured with varying depths of focus, allowing an image's depth of field to be adjusted during post processing. In-display cameras can also be used for user authentication, touch detection and three-dimensional gesture recognition. Thermal sensors located within the display area allow for control of the display temperature, improved control over system performance, and compensation for micro-LED degradation that can occur due to aging or increased temperature. Microlens assemblies located above pixels can adjust the viewing cone angle of the display or a portion of the display and microassemblies located under individual pixels or pixel arrays can adjust a viewing angle.

Abstract: A display comprising a display substrate comprising a front side; a plurality of pixels located on the front side of the display substrate, the plurality of pixels defining a display area; and an antenna array comprising a plurality of antennas located on the front side of the display substrate and within the display area.

Abstract: Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage than the power supply and to provide power to the first charge pump during an active mode of the flash memory array.

Abstract: Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage than the power supply and to provide power to the first charge pump during an active mode of the flash memory array.

Abstract: Techniques that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. In an example embodiment, a method of operating a memory device comprises monitoring on the power supply level applied to the device and determining a corresponding number of bitlines that the device can activate at the same time, generating a control signal based on the number of bitlines, and using the control signal to activate a portion of the memory device corresponding to the determined number of bitlines.

Abstract: Techniques that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. In an example embodiment, a method of operating a memory device comprises monitoring on the power supply level applied to the device and determining a corresponding number of bitlines that the device can activate at the same time, generating a control signal based on the number of bitlines, and using the control signal to activate a portion of the memory device corresponding to the determined number of bitlines.

Abstract: Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.

Abstract: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.

Abstract: An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.

Abstract: Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a “source” bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.

Abstract: Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.

Abstract: Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a “source” bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.

Abstract: Systems and methods that control the switching transition times or profile of a ramped voltage write signal used for programming or erasing at least a wordline of an array of multi-bit and/or multi-level flash memory cells are provided. In one embodiment, this goal is accomplished by applying a ramped or otherwise controlled profile write voltage to the flash memory cells in order to avoid disturb issues to the unselected (non-targeted) neighboring memory cells, which preserves the existing state of the neighboring cells while keeping the design as compact and manageable as possible yet maintains a high write speed. The systems and method are applicable to, and reliable for various memory technologies, since the size of the steps or other such functional transitions of the ramped voltage profile can be adjusted or trimmed to any level of resolution required.