Abstract: A device for transmitting data to a further device is arranged for transmitting a first class of data as a guaranteed stream of data-units, and for transmitting a second class of data-units on a best effort basis. The device starts the transmission of a burst of data-units which belong to the second class at a point in time where the remaining time interval until the start of the next burst of first-class data minus the required time for transmitting the burst of second-class of data is less than a predetermined time.

Abstract: A data processor system includes a first data processor unit for transmitting data units to a second data processor unit and a retry buffer for temporarily storing transmitted data units. The second data processor unit receives the transmitted data and includes an error detector for detecting an error in the received data. When an error is detected, the first data processor unit is notified and a controller causes a data selector to select data from a retry buffer. The first data processor unit limits retransmission of a data unit to a predetermined maximum number of times irrespective of whether the data unit is correctly received or not. This allows for an undisturbed flow of streaming data with an increased reliability.

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.

Abstract: A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

Abstract: A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N; IM). The memory controller (SMC) comprises a first interface (PI) for connecting the memory controller (SMC) to the network (N; IM). The first interface (PI) is arranged for receiving and transmitting data streams (ST1-ST4). A streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N; IM) and the memory (MEM). Said streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4). A buffer managing unit (BMU) is provided for managing a temporarily storing of data streams (ST1-ST4) in the buffer (B) in a first and second operation mode (1OM; 2OM). In the first operation mode (1OM), data from the data streams (ST1-ST4) to be stored in the memory (MEM) are temporarily stored in the buffer (B) until a portion of the buffer (B) is occupied.

Abstract: In order to provide a switch device (100; 100?) connecting at least one first point (10, 12), in particular connecting at least one source device and/or at least another switch device, to at least one second point (20, 22, 24), in particular to at least one destination device and/or to at least another switch device, the switch device (100; 100?) comprising at least one virtual channel (30, 32), wherein it is possible to arbitrate and/or differentiate data, in particular data packets or data streams, being transmitted within the same virtual channel (30, 32), it is proposed that the switch device (100; 100?) comprises at least two ports (40, 42), in particular input ports, for receiving and/or at least two ports (50, 52), in particular output ports, for sending the data, in particular the data packet or data stream, the ports (40, 42, 50, 52) being respectively assigned to the virtual channel (30, 32).

Abstract: A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (ST1-ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (ST1-ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts.

Abstract: A data processor system is described comprising a first and a second data processor unit (PU1, PU2). The first data processor unit (PU1) has a data source (SW1, IP11, IP 12) for providing data units for transmission to the second data processor unit (PU2) and a retry buffer (RBUF) for temporarily storing transmitted data units. It is provided with a data selector (RSEL) for selecting data units from the data source or from the retry buffer, and a controller (RCTRL) for controlling the data selector, as well as an output (T1x) for providing data selected for transmissions. The second data processor unit (PU2) has an input (R1x) for receiving the transmitted data and an output (PU20) for further transmitting the received data to a third data processor unit. It also has an input buffer (IBUF) coupled to the input, for temporarily storing the received data.

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.

Abstract: A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

Abstract: A device (D1) for transmitting data to a further device (D2) is arranged for transmitting a first class of data (GT) as a guaranteed stream of data-units, and for transmitting a second class of data-units (BE) on a best effort basis. The device (D1) starts the transmission of a burst of data-units which belong to the second class (BE) at a point in time (t2_start) where the remaining time interval (t1_start) until the start of the next burst of first-class data (GT) minus the required time (t2_burst) for transmitting the burst of second-class of data is less than a predetermined time (Tp).

Abstract: A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N; IM). The memory controller (SMC) comprises a first interface (PI) for connecting the memory controller (SMC) to the network (N; IM). The first interface (PI) is arranged for receiving and transmitting data streams (ST1-ST4). A streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N; IM) and the memory (MEM). Said streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4). A buffer managing unit (BMU) is provided for managing a temporarily storing of data streams (ST1-ST4) in the buffer (B) in a first and second operation mode (1OM; 2OM). In the first operation mode (1OM), data from the data streams (ST1-ST4) to be stored in the memory (MEM) are temporarily stored in the buffer (B) until a portion of the buffer (B) is occupied.

Abstract: In order to provide a switch device (100; 100?) connecting at least one first point (10, 12), in particular connecting at least one source device and/or at least another switch device, to at least one second point (20, 22, 24), in particular to at least one destination device and/or to at least another switch device, the switch device (100; 100?) comprising at least one virtual channel (30, 32), wherein it is possible to arbitrate and/or differentiate data, in particular data packets or data streams, being transmitted within the same virtual channel (30, 32), it is proposed that the switch device (100; 100?) comprises at least two ports (40, 42), in particular input ports, for receiving and/or at least two ports (50, 52), in particular output ports, for sending the data, in particular the data packet or data stream, the ports (40, 42, 50, 52) being respectively assigned to the virtual channel (30, 32).