Patents by Inventor Ewa M. Kubalska

Ewa M. Kubalska has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8659601
    Abstract: A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: February 25, 2014
    Assignee: NVIDIA Corporation
    Inventors: Justin Michael Mahan, Edward A. Hutchins, Ewa M. Kubalska, James T. Battle
  • Patent number: 7737994
    Abstract: A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: June 15, 2010
    Assignee: Oracle America, Inc.
    Inventors: Michael A. Wasserman, Ewa M. Kubalska, Nathaniel David Naegle, Brian D. Emberling, Paul R. Ramsey, Mark E. Pascual
  • Patent number: 7027064
    Abstract: An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: April 11, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, Ewa M. Kubalska, Yan Yan Tang
  • Patent number: 7023444
    Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 4, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian D. Emberling, Michael G. Lavelle, Assana M. Fard, Nandini Ramani, David C. Kehlet, Michael A. Wasserman, Ewa M. Kubalska, Mark E Pascual
  • Patent number: 6943797
    Abstract: A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: September 13, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael A. Wasserman, Ewa M. Kubalska, Brian D. Emberling
  • Patent number: 6924820
    Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. To overcome fragmentation problems, the system's sample evaluation hardware may be configured to over-evaluate samples each clock cycle. Since a number of the samples will typically not survive evaluation because they will be outside the primitive being rendered, the remaining surviving samples may be combined into sets, with one set being forwarded to subsequent pipeline stages each clock cycle in order to attempt to keep the pipeline utilization high.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 2, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Nandini Ramani, David C. Kehlet, Michael G. Lavelle, Mark E. Pascual, Ewa M. Kubalska, Yi-Ming Tian
  • Patent number: 6895458
    Abstract: A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: May 17, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Ewa M. Kubalska, Lisa Grenier, Yan Yan Tang, Elena M. Ing
  • Patent number: 6885375
    Abstract: A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian D. Emberling, Ewa M. Kubalska, Steve Kurihara, Anthony S. Ramirez, Andre J. Gaytan
  • Patent number: 6859209
    Abstract: A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: February 22, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, Brian D. Emberling, Ranjit S. Oberoi, Deron D. Johnson, Ewa M. Kubalska
  • Patent number: 6847369
    Abstract: A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: January 25, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, Ewa M. Kubalska, Anthony S. Ramirez, Huang Pan
  • Patent number: 6842851
    Abstract: A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: January 11, 2005
    Assignee: Sun Microsytems, Inc.
    Inventors: Wayne Eric Burk, Ewa M. Kubalska, Brian D. Emberling
  • Publication number: 20040263520
    Abstract: A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Michael A. Wasserman, Ewa M. Kubalska, Brian D. Emberling
  • Patent number: 6833834
    Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: December 21, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael A. Wasserman, Michael G. Lavelle, David C. Kehlet, Yan Yan Tang, Ewa M. Kubalska
  • Patent number: 6833831
    Abstract: A method and system for synchronizing data streams and transferring control of resources between two processes in a graphics processor is described. The method allows for completion of pending operations of a first process in a manner that ensures the first process may be restarted without loss of data or process sequence. The processing pipeline is allowed to complete normal execution of all process operations required to reach a first process step that may be interrupted. The second process is initiated when the interruption of the first process is verified. Upon completion of the second process, the first process is reactivated at the next process step in sequence.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: December 21, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian D. Emberling, Ewa M. Kubalska
  • Patent number: 6812929
    Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: November 2, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, Ewa M. Kubalska, Yan Yan Tang
  • Patent number: 6803916
    Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: October 12, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Nandini Ramani, David C. Kehlet, Ewa M. Kubalska, Michael G. Lavelle, Michael A. Wasserman, Kevin Tang, Yan Yan Tang
  • Publication number: 20040183807
    Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Inventors: Brian D. Emberling, Michael G. Lavelle, Assana M. Fard, Nandini Ramani, David C. Kehlet, Michael A. Wasserman, Ewa M. Kubalska, Mark E. Pascual
  • Patent number: 6795078
    Abstract: A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 21, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, Ewa M. Kubalska, Yan Y. Tang
  • Patent number: 6781406
    Abstract: An integrated circuit including logic for testing internal operation of the integrated circuit. The integrated circuit may comprise a plurality of internal functional blocks coupled by a plurality of internal buses. The integrated circuit may also comprise a set of test control input pins and a set of test output pins comprised on the integrated circuit. The integrated circuit may comprise selection logic. The selection logic comprises inputs coupled to various ones of the internal buses, an output coupled to the set of test output pins, and a select input coupled to receive select signals from the set of test control input pins. The selection logic is operable to select internal bus signals from an internal bus based on the select signals from the test control input pins, and the selection logic is configured to output the selected internal bus signals to the set of test output pins.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: August 24, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian D. Emberling, Ewa M. Kubalska
  • Patent number: 6778179
    Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: August 17, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, Ewa M. Kubalska, Yan Yan Tang