Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body.

Abstract: A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location.

Abstract: An integrated circuit for a dynamic semiconductor random access memory, constructed of complementary transistors, has memory cells connected to bit lines by way of individual selection transistors of a first channel type, the operation of which is controlled by word lines. The voltage on the word lines is controlled by a first switching transistor of a second channel type, controlled by the output of a decoder. The first switching transistor is connected between the word line and a selection voltage which alternates between two voltage values of different operational signs, and the gate of the first switching transistor is connected through a capacitor to the selection voltage and through a second switching transistor having its gate at reference potential, to the output of the decoder.

Abstract: An integrated circuit for emitting a clock voltage V.sub.A which alternates between positive and negative voltage levels with the clock voltage being controllable by means of a unipolar clock voltage V.sub.E and wherein the circuit is a very simple small semiconductor arrangement which has three series connected field effect transistors T1, T2 and T3 with the first end of the series arrangement receiving a first reference voltage and the other end of the series arrangement receiving a second reference voltage. The first and second field effect transistors 1 and 2 or first and second channel types and have gate terminals which are commonly connected to the control input V.sub.E and the junction point 3 of the first two field effect transistors T1 and T2 connected to the output terminal and also connected by way of a capacitor to the gate of the third field effect transistor T3 which is of the first channel type.

Abstract: A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.