Abstract: A motor-driven chair has a central drive wheel located beneath the seat and linked so as to be aligned with the facing direction of the seat. A user turns the direction of motion by rotating the seat relative to a surrounding stabilizer assembly so as to turn the seat and the drive wheel towards a direction in which he wishes to move. A suspension arrangement maintains a desired distribution of user load between the drive wheel and the stabilizer assembly. A combination of fixed-axis wheels with castered wheels provides angular anchoring of the stabilizer assembly to facilitate the seat steering process. The entire structure is preferably foldable for easy transportation and storage.

Abstract: A motor-driven chair has a central drive wheel located beneath the seat and linked so as to be aligned with the facing direction of the seat. A user turns the direction of motion by rotating the seat relative to a surrounding stabilizer assembly so as to turn the seat and the drive wheel towards a direction in which he wishes to move. A suspension arrangement maintains a desired distribution of user load between the drive wheel and the stabilizer assembly. A combination of fixed-axis wheels with castered wheels provides angular anchoring of the stabilizer assembly to facilitate the seat steering process. The entire structure is preferably foldable for easy transportation and storage.

Abstract: A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.

Abstract: A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.