Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypas sable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypas sable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

Abstract: A data structure depicting unicast queues comprises a Structure Pointer memory for storing pointers to a location in memory of a segment of a packet associated with a respective queue. A Structure Pointer points to a record in the Structure Pointer memory associated with a successive segment, and a packet indicator indicates whether the segment is a first and/or a last segment in the packet. A Head & Tail memory stores an address in the Structure Pointer memory of the first and last packets in the queue, and a free structure memory points to a next available memory location in the Structure Pointer memory. To support multicast queues the data structure, a multiplicity memory stores the number of destinations to which a respective queue is to be routed. A scheduling method and system using such a data structure are also described.

Abstract: A method for transmitting data between line cards in a distributed network switching system, through a switch fabric which is separated from said line cards, said method comprising receiving at said switch fabric information regarding queues of data packets that have arrived at said line cards and are waiting to be transmitted therefrom, recording said information at one or more databases located in said switch fabric, computing in said switch fabric a suitable array of connections between said line cards according to the information recorded at said one or more databases, providing instructions to said line cards regarding the data that is allowed to be transmitted therefrom, establishing a physical array of connections in said switch fabric to allow said transmission, and updating said one or more databases at said switch fabric accordingly, wherein said updating of the one or more databases occurs before said transmission of data from the input line cards takes place, such that the updated information stor

Abstract: A method and distributed scheduler for use therewith has at least two clusters of source port modules, each tracking all queues associated with a respective input-node and relating to a respective subset of available input-nodes. Each source port module receives available output-nodes, and generates a weight for each queue therein. Each source port module generates at least one request relating to the highest weight serviceable queue. The respective requests of each source port module are accumulated, and for each cluster of source port modules, the request is chosen for which no two requests relate to the same input-node, and for each output-node, the chosen requests have highest weight. The highest weight request from all clusters is determined in respect of each output node receiving requests from one or more input nodes. A grant is sent to the input-node having the highest weight request.