Patents by Inventor Eyal Segev

Eyal Segev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230280282
    Abstract: A method that may include performing first measurements of the height differences between the bumps and the corresponding areas, by illuminating the bumps and the corresponding areas with first radiation; wherein the first measurements are subjected to first measurement errors resulting from a virtual penetration of the first illumination into the layer; wherein each bump has a corresponding area that is proximate to the bump; preforming second measurements of thickness of the layer at the corresponding areas; wherein at least some of the first measurements are executed in parallel to an executing of at least some of the second measurements; determining first measurement errors, based on the second measurements; and determining the height differences between the bumps and the corresponding areas based on the first measurements and the first measurements errors.
    Type: Application
    Filed: July 11, 2021
    Publication date: September 7, 2023
    Applicant: CAMTEK Ltd.
    Inventor: Eyal Segev
  • Publication number: 20230228559
    Abstract: A method for measuring height differences between tops of multiple bumps of an upper surface of a layer, the method may include performing first measurements of the height differences between the bumps and the corresponding areas, by illuminating the bumps and the corresponding areas with first radiation; wherein the first measurements are subjected to first measurement errors; and determining the height differences between the bumps and the corresponding areas based on the first measurements and the first measurements errors.
    Type: Application
    Filed: July 11, 2021
    Publication date: July 20, 2023
    Applicant: CAMTEK Ltd.
    Inventor: Eyal Segev
  • Patent number: 10734340
    Abstract: A method for estimating a thickness related to multiple conductive structural elements of an object, the method includes estimating a height difference between an upper surface of a conductive structural element and an upper surface of a photoresists layer portion that surrounds the conductive structural element, to provide multiple height differences; estimating thicknesses of the multiple photoresists layer portions, based at least on the second part of the emitted radiation; and calculating thickness values related to the multiple conductive structural elements, wherein the calculating is based at least on the multiple height differences and on the estimated thickness of the multiple photoresists layer portions.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 4, 2020
    Assignee: CAMTEK LTD.
    Inventor: Eyal Segev
  • Publication number: 20190355688
    Abstract: A method for estimating a thickness related to multiple conductive structural elements of an object, the method includes estimating a height difference between an upper surface of a conductive structural element and an upper surface of a photoresists layer portion that surrounds the conductive structural element, to provide multiple height differences; estimating thicknesses of the multiple photoresists layer portions, based at least on the second part of the emitted radiation; and calculating thickness values related to the multiple conductive structural elements, wherein the calculating is based at least on the multiple height differences and on the estimated thickness of the multiple photoresists layer portions.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 21, 2019
    Inventor: EYAL SEGEV
  • Patent number: 8754668
    Abstract: An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: June 17, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yossi Amon, Dimitri Akselrod, Eyal Segev
  • Patent number: 8111945
    Abstract: A method, a system and a computer program product for generating a blended picture, the system includes: a storage unit, adapted to store pixels of a first picture, pixels of a second picture and alpha data; and a device, coupled to the storage unit via at least one data channel; wherein the device includes: a relevancy determination module, that is adapted to determine a relevancy of pixels of at least one of the first picture and the second picture based upon values of alpha data associated with the pixels of the first picture; wherein the alpha data represents a degree of transparency of the pixels of the first picture to be overlaid over the second picture; an access controller, coupled to the relevancy determination module, adapted to prevent a transfer of irrelevant pixels from the storage unit; and a blending unit that is coupled to the access controller, adapted to provide a blended picture in response to values of the alpha data, by blending relevant pixels of the first and second picture.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: February 7, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Roy Kehat, Eran Barnea, Oskar Pelc, Eyal Segev
  • Publication number: 20100019794
    Abstract: An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
    Type: Application
    Filed: November 22, 2004
    Publication date: January 28, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yossi Amon, Dimitri Akselrod, Eyal Segev
  • Publication number: 20100021081
    Abstract: A method, a system and a computer program product for generating a blended picture, the system includes: a storage unit, adapted to store pixels of a first picture, pixels of a second picture and alpha data; and a device, coupled to the storage unit via at least one data channel; wherein the device includes: a relevancy determination module, that is adapted to determine a relevancy of pixels of at least one of the first picture and the second picture based upon values of alpha data associated with the pixels of the first picture; wherein the alpha data represents a degree of transparency of the pixels of the first picture to be overlaid over the second picture; an access controller, coupled to the relevancy determination module, adapted to prevent a transfer of irrelevant pixels from the storage unit; and a blending unit that is coupled to the access controller, adapted to provide a blended picture in response to values of the alpha data, by blending relevant pixels of the first and second picture.
    Type: Application
    Filed: July 25, 2008
    Publication date: January 28, 2010
    Inventors: Roy Kehat, Eran Barnea, Oskar Pelc, Eyal Segev