Abstract: An electronic apparatus receives a noisy signal and produces and stores hard data and soft data. It has a first portion (210, 310) for receiving electromagnetic signals and producing hard data and soft data, and a second portion (200, 300) for storing soft data and hard data concerning a particular signal at a single location in a memory bank (270, 370), preferably at the same memory address. Hard data and soft data can be stored in consecutive memory cells. Hard data can overlap soft data. If hard data overlaps soft data, it preferably overlaps soft data least significant bits. The second portion (200, 300) has a memory bank (270, 370), a controller (260, 360) and also can have a synchronizer (390) for synchronizing between soft data and hard data concerning the same input signal.

Abstract: The present invention relates to memory and methods for storing/retrieving data in/from the memory that is accessed by at least two distinct data uses of different actual word widths. A memory for storing addressable binary data comprises a data storage organized in rows and columns of bit array cells, row address decoder and driver for addressing a selected row of bit array cells, column drivers for driving selected columns of bit array cells, and a bus switch port for selectively transferring data between the data storage and a first data bus with a first bus word width p and a second data bus with a second bus word width q smaller than the first bus word width p.

Abstract: According to the present invention, an LFSR (300) has a propagation path (30) of serially coupled stages (65) and gates (80-3, 80-4), a feedforward path (10) of gates (80-1) and a feedback path (20) of gates (80-2). Depending on control signals (P, B, M), the gates (80-1, 80-2, 80-3, 80-4) are either active gates and operate as xor-gates or passive gates and operate as transfer gates. Feedforward and feedback signals are derived from input and output signals and can be supplied to any stage (65), so that characteristic polynomials of the input-output function are variable. The LFSR can fully or partly operate as a TYPE 1 or TYPE 2 LFSR which enables the execution of different algorithms on one hardware base.

Abstract: The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.

Abstract: The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.

Abstract: Oscillation of the output (16, 17) of an integrated circuit output buffer (43) is automatically damped by sensing ground lead (18) transients as the buffer output (16, 17) changes, and when the ground lead (18) swing is large enough, using the sensed change to apply a turn-off signal of the appropriate polarity to a transistor (N1) serially placed in the output buffer (43) to add resistance during the transition. The added resistance damps out the oscillations quickly to prevent rebound of the buffer output voltage past the logic transition threshold (Vol). An RC time constant (R1, C1) controls the duration of the added resistance which disappears after the transition is complete. The action of a damping control circuit (45) is speed dependent so that greater damping is provided for fast transitions when oscillations would be more sever and no damping during slow transitions when damping is not needed.