Abstract: Technologies are generally described for power channel monitoring in multicore processors. A power management system can be configured to monitor the power channels supplying individual cores within a multicore processor. A power channel monitor can provide a direct measurement of power consumption for each core. The power consumption of individual cores can indicate which cores are encountering higher or lower usage. The usage determination can be made without sending any data messages to, or from, the cores being measured. The determined usage load being serviced by each processor core may be used to adjust power and/or clock signals supplied to the cores.

Abstract: Technologies are generally described for runtime management of processes on multicore processing systems using process affinity graphs. Two or more processes may be determined to be related when the processes share interprocess messaging traffic. These related processes may be allocated to neighboring or nearby processor cores within a multicore processor using graph theory techniques as well as communication analysis techniques to evaluate interprocess communication needs. Process affinity graphs may be established to aid in determining grouping of processors and evaluating interprocess message traffic between groups of processes. The process affinity graphs may be based upon process affinity scores determined by monitoring and analyzing interprocess messaging traffic. Process affinity graphs may further inform splitting process affinity groups from one core onto two or more cores.

Abstract: A process for fabricating a MEMS device with movable comb teeth and stationary comb teeth. A single mask is used to define, during a series of processing steps, the location and width of both movable comb teeth and stationary comb teeth so as to assure self alignment of the comb teeth. MEMS devices are fabricated from a single multi-layer semi-conductor structure of semiconductor material and insulator material. In a preferred embodiment the process is employed to provide a MEMS mirror device having a movable structure, a movable frame, a first set of two torsional members, a first set of at least four comb drives, an outer fixed frame structure, a second set of two torsional members, and a second set of at least four comb drives.

Abstract: Technologies are generally described for runtime optimization adjusted dynamically according to changing costs of one or more system resources. Multicore systems may encounter dynamic variations in performance associated with the relative cost of related system resources. Furthermore, multicore systems can experience dramatic variations in resource availability and costs. A dynamic registry of system resource costs can be utilized to guide dynamic optimization. The relative scarcity of each resource can be updated dynamically within the registry of system resource costs. A runtime code generating loader and optimizer may be adapted to adjust optimization according to the resource cost registry. Information regarding system resource costs can support optimization tradeoffs based on resource cost functions.

Abstract: Technologies are generally described for parallel dynamic optimization using multicore processors. A runtime compiler may be adapted to generate multiple instances of executable code from a portable intermediate software module. The various instances of executable code may be generated with variations of optimization parameters such that the code instances each express different optimization attempts. A multicore processor may be leveraged to simultaneously execute some, or all, of the various code instances. Preferred optimization parameters may be determined from the executable code instances that may correctly complete in the least time, or may use the least amount of memory, or that may prove superior according to some other fitness metric. Preferred optimization parameters may be used to seed future optimization attempts. Output generated from the preferred instances may be used as soon as the first instance correctly completes block.

Abstract: Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.

Abstract: A process for fabricating a MEMS device with movable comb teeth and stationary comb teeth. A single mask is used to define, during a series of processing steps, the location and width of both movable comb teeth and stationary comb teeth so as to assure self alignment of the comb teeth. MEMS devices are fabricated from a single multi-layer semi-conductor structure of semiconductor material and insulator material. In a preferred embodiment the process is employed to provide a MEMS mirror device having a movable structure, a movable frame, a first set of two torsional members, a first set of at least four comb drives, an outer fixed frame structure, a second set of two torsional members, and a second set of at least four comb drives.

Abstract: Technologies are generally described for power channel monitoring in multicore processors. A power management system can be configured to monitor the power channels supplying individual cores within a multicore processor. A power channel monitor can provide a direct measurement of power consumption for each core. The power consumption of individual cores can indicate which cores are encountering higher or lower usage. The usage determination can be made without sending any data messages to, or from, the cores being measured. The determined usage load being serviced by each processor core may be used to adjust power and/or clock signals supplied to the cores.

Abstract: Technologies are generally described for runtime management of processes on multicore processing systems using process affinity graphs. Two or more processes may be determined to be related when the processes share interprocess messaging traffic. These related processes may be allocated to neighboring or nearby processor cores within a multicore processor using graph theory techniques as well as communication analysis techniques to evaluate interprocess communication needs. Process affinity graphs may be established to aid in determining grouping of processors and evaluating interprocess message traffic between groups of processes. The process affinity graphs may be based upon process affinity scores determined by monitoring and analyzing interprocess messaging traffic. Process affinity graphs may further inform splitting process affinity groups from one core onto two or more cores.

Abstract: Technologies are generally described for runtime optimization adjusted dynamically according to changing costs of one or more system resources. Multicore systems may encounter dynamic variations in performance associated with the relative cost of related system resources. Furthermore, multicore systems can experience dramatic variations in resource availability and costs. A dynamic registry of system resource costs can be utilized to guide dynamic optimization. The relative scarcity of each resource can be updated dynamically within the registry of system resource costs. A runtime code generating loader and optimizer may be adapted to adjust optimization according to the resource cost registry. Information regarding system resource costs can support optimization tradeoffs based on resource cost functions.

Abstract: Technologies are generally described for parallel dynamic optimization using multicore processors. A runtime compiler may be adapted to generate multiple instances of executable code from a portable intermediate software module. The various instances of executable code may be generated with variations of optimization parameters such that the code instances each express different optimization attempts. A multicore processor may be leveraged to simultaneously execute some, or all, of the various code instances. Preferred optimization parameters may be determined from the executable code instances that may correctly complete in the least time, or may use the least amount of memory, or that may prove superior according to some other fitness metric. Preferred optimization parameters may be used to seed future optimization attempts. Output generated from the preferred instances may be used as soon as the first instance correctly completes block.

Abstract: Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.

Abstract: In certain embodiments, a MEMS actuator is provided comprising a frame and a movable structure coupled to the frame. A vertical comb drive is provided between the frame and the movable structure to actuate the movable structure.

Abstract: In one implementation, a method for operating a plurality of MEMS devices including applying a magnitude of a selected actuation signal equal to a first substantially constant magnitude to an actuator to cause a movable structure to begin to accelerate from a first position to impact a motion stop at a second position. The method also includes decreasing the magnitude of the selected actuation signal in a first manner. The method further includes varying at least one of a start time and a duration of the decreasing magnitude of the selected actuation signal and observing a settling time of the movable structure in response to the step of varying. In some implementations, the method includes ascertaining a range of values for the start times and the corresponding durations for each of the plurality of MEMS devices that are capable of providing settling times of the movable structure in conformance with a predetermined specification based on the steps of varying and observing.

Abstract: A modular three-dimensional (3D) optical switch that is scalable and that provides monitor and control of MEMS mirror arrays. A first switch module includes an array of input channels. Light beams received from the input channels are directed toward a first wavelength selective mirror. The light beams are reflected off of the first wavelength selective mirror and onto a first array of moveable micromirrors. The moveable micromirrors are adjusted so that the light beams reflect therefrom and enter a second switch module where they impinge upon a second array of moveable micromirrors. The light beams reflect off of the second array of moveable micromirrors and impinge upon a second wavelength selective mirror. The light beams reflect off of the second wavelength selective mirror and into an array of output channels. The alignment or misalignment of a data path through the switch is detected by directing two monitor beams through the data path, one in the forward direction and one in the reverse direction.

Abstract: In one embodiment, a MEMS apparatus having a MEMS array including a plurality of MEMS devices is provided. In some embodiments, each of the plurality of MEMS devices includes a movable structure and a second structure. In addition, in some embodiments, a plurality of signal sources are coupled to the plurality of MEMS devices so as to be capable of supplying actuation signals for actuating the movable structure to impact the second structure. Further, in some embodiments, at least one processor is coupled to the plurality of signal sources to control the actuation signals, and is configured such that each of the plurality of MEMS devices is provided with a corresponding custom actuation signal.