Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

Abstract: Apparatuses and methods can be related to reducing memory device overhead using artificial intelligence (AI). Reducing overhead can include receiving file metadata of a data file and device metadata of the memory device. Based on the file metadata and the device metadata, a number of indicators can be selected to provide an indication of an expected use of the data file in the memory device. The number of indicators can be provided to the memory device. The data file can be stored with different data files having matching indicators corresponding thereto.

Abstract: A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.

Abstract: Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.

Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.

Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

Abstract: A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.

Abstract: A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.

Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

Abstract: Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.

Abstract: Apparatuses and methods can be related to reducing memory device overhead using artificial intelligence (AI). Reducing overhead can include receiving file metadata of a data file and device metadata of the memory device. Based on the file metadata and the device metadata, a number of indicators can be selected to provide an indication of an expected use of the data file in the memory device. The number of indicators can be provided to the memory device. The data file can be stored with different data files having matching indicators corresponding thereto.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

Abstract: An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: In one general embodiment, a computer-implemented method includes determining attributes of a plurality of objects in an object-based storage environment, grouping the objects into clusters based on similarities of the attributes using a clustering algorithm, storing indication of which objects are in which clusters, detecting occurrence of a trigger event associated with an object, determining to which cluster the object belongs using the clustering algorithm in response to detecting the trigger event, and performing a deduplication process for the object against other objects in the cluster to which the object belongs. In another general embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.

Abstract: In one general embodiment, a computer-implemented method includes determining attributes of a plurality of objects in an object-based storage environment, grouping the objects into clusters based on similarities of the attributes using a clustering algorithm, storing indication of which objects are in which clusters, detecting occurrence of a trigger event associated with an object, determining to which cluster the object belongs using the clustering algorithm in response to detecting the trigger event, and performing a deduplication process for the object against other objects in the cluster to which the object belongs. In another general embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.