Abstract: One example includes a switching power converter circuit. The circuit includes a gate driver configured to generate at least one switching signal in response to a feedback signal. The circuit also includes a feedback stage configured to generate the feedback signal based on an amplitude of an output voltage at an output. The circuit further includes a power stage including at least one switch and a transformer. The at least one switch can be controlled via the respective at least one switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current through a secondary winding of the transformer to generate the output voltage. The power stage further includes a self-driven synchronous rectifier stage coupled to the secondary winding to conduct the secondary current from a low voltage rail through the secondary winding.

Abstract: Aspects include a power supply system. The system includes an oscillator system configured to generate a clock signal at a clock node. The oscillator system includes a comparator configured to compare a first variable voltage at a first comparator node and a second variable voltage at a second comparator node. The first and second variable voltages can have respective magnitudes that are based on a state of the clock signal. The system also includes a pulse-width modulation (PWM) generator configured to generate a PWM signal based on an error voltage and the clock signal. The system further includes a power stage configured to generate an output voltage based on the PWM signal.

Abstract: One aspect includes power supply systems. The system includes an error amplifier system configured to generate an error voltage based on a feedback voltage of the power supply system relative to a reference voltage. The system also includes a PWM generator comprising a comparator configured to generate a PWM signal based on the error voltage and a ramp signal. The system further includes a power stage configured to generate the output voltage based on the PWM signal, the power stage comprising a transconductance amplifier configured to generate a temperature-compensated sense current associated with a magnitude of an output current associated with power stage. The ramp signal being generated based on the temperature-compensated sense current.

Abstract: Aspects of the present invention include a power supply system comprising a plurality of power supplies. Each of the power supplies can include an oscillator system configured to generate a clock signal at a clock node. Each of the power supplies can include an error amplifier configured to generate an error voltage at an error amplifier output node. Each of the power supplies can also include a pulse-width modulation (PWM) generator configured to generate a PWM switching signal based on an error voltage and the clock signal. Each of the power supplies can further include a power stage configured to generate an output voltage based on the PWM switching signal.

Abstract: One example of generating a clock signal via an oscillator system includes increasing a first comparison voltage at a first comparison node from a first magnitude to a second magnitude in response to a clock signal. A second comparison voltage is increased at a second comparison node from the first magnitude to the second magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage. The first comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The second comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage.

Abstract: One example of generating a clock signal via an oscillator system includes increasing a first comparison voltage at a first comparison node from a first magnitude to a second magnitude in response to a clock signal. A second comparison voltage is increased at a second comparison node from the first magnitude to the second magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage. The first comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The second comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage.

Abstract: One aspect includes power supply systems. The system includes an error amplifier system configured to generate an error voltage based on a feedback voltage of the power supply system relative to a reference voltage. The system also includes a PWM generator comprising a comparator configured to generate a PWM signal based on the error voltage and a ramp signal. The system further includes a power stage configured to generate the output voltage based on the PWM signal, the power stage comprising a transconductance amplifier configured to generate a temperature-compensated sense current associated with a magnitude of an output current associated with power stage. The ramp signal being generated based on the temperature-compensated sense current.

Abstract: Aspects include a power supply system. The system includes an oscillator system configured to generate a clock signal at a clock node. The oscillator system includes a comparator configured to compare a first variable voltage at a first comparator node and a second variable voltage at a second comparator node. The first and second variable voltages can have respective magnitudes that are based on a state of the clock signal. The system also includes a pulse-width modulation (PWM) generator configured to generate a PWM signal based on an error voltage and the clock signal. The system further includes a power stage configured to generate an output voltage based on the PWM signal.

Abstract: Aspects include power supply systems. An error amplifier can generate an error voltage based on feedback associated with an output voltage to a reference voltage. A PWM generator can generate a PWM signal based on the error voltage. A power stage can generate the output voltage based on the PWM signal. The power stage can include a transconductance amplifier that generates a temperature-compensated sense current associated with a magnitude of an output current. An output voltage tuning circuit sets a desired magnitude of the output voltage based on at least one digital signal to adjust the reference voltage and the feedback voltage. An oscillator system generates a clock signal based on repeatedly charging and discharging a capacitor based on the clock signal and a comparator that compares the capacitor voltage and a second voltage having a magnitude that changes based on the state of the clock signal.

Abstract: Aspects of the present invention include a power supply system comprising a plurality of power supplies. Each of the power supplies can include an oscillator system configured to generate a clock signal at a clock node. Each of the power supplies can include an error amplifier configured to generate an error voltage at an error amplifier output node. Each of the power supplies can also include a pulse-width modulation (PWM) generator configured to generate a PWM switching signal based on an error voltage and the clock signal. Each of the power supplies can further include a power stage configured to generate an output voltage based on the PWM switching signal.

Abstract: Aspects include power supply systems. An error amplifier can generate an error voltage based on feedback associated with an output voltage to a reference voltage. A PWM generator can generate a PWM signal based on the error voltage. A power stage can generate the output voltage based on the PWM signal. The power stage can include a transconductance amplifier that generates a temperature-compensated sense current associated with a magnitude of an output current. An output voltage tuning circuit sets a desired magnitude of the output voltage based on at least one digital signal to adjust the reference voltage and the feedback voltage. An oscillator system generates a clock signal based on repeatedly charging and discharging a capacitor based on the clock signal and a comparator that compares the capacitor voltage and a second voltage having a magnitude that changes based on the state of the clock signal.

Abstract: A double forward DC-to-DC converter with soft-PWM switching provides two voltage pulses to the output low-pass filter within one switching cycle (hence, the name double forward). The double forward DC to DC converter includes a transformer having a single primary winding and a two secondary windings. A main switch, under the control of a PWM control circuit, is connected is series with the primary winding. An auxiliary switch is coupled across with the main switch by way of a resonant capacitor. The resonant capacitor and auxiliary switch are used to automatically reset the transformer core while the main switch is on back to the voltage source connected to the transformer primary. A diode and snubber capacitor is connected across the drain-source terminals for both the main and auxiliary switches for minimizing switching losses. The current mirror used in prior art is abandoned in order to avoid the locked-up mode of operation.

Abstract: A full-bridge converter 10 is provided which performs soft switching based on pulse width modulated switching signals. The, converter 10 includes a primary side 12 and a secondary side 14 interconnected through a transformer 13. The primary side 12 includes a power source connected in parallel with leading and trailing legs 20 and 22, respectively. The leading leg 20 includes first and second switching transistors Q1 and Q2 connected in series, while the trailing leg 22 includes third and fourth switching transistors Q3 and Q4 connected in series. The switching transistors Q1-Q4 each include parasitic diodes D1-D4 and parasitic capacitances C1-C4. A control circuit 15 generates pulse width modulated (PWM) switching signals applied to gates G1-G4 of the transistors Q1-Q4. The control circuit 15 simultaneously turns on transistors Q1 and Q3 during a first energy transfer stage and simultaneously turns on transistors Q2 and Q4 during a second energy transfer stage.