Abstract: A battery and straps for a battery are disclosed. The battery according to various embodiments comprises a number of straps which connect a number of battery cells in series. The battery straps may pass through cutouts provided in a cell divider wall. The cutouts and straps may define a common headspace. The battery may have five connecting straps and two end straps.

Abstract: Disclosed is a battery comprising a cover; a housing having a base, two side walls, and two end walls; a cell wall spanning between the first and second side walls defining two cells; a battery element provided within a cell, the battery element having a bottom; an element bottom gap, the element bottom gap defined in a first and second dimension by the cell width and length, and a third dimension by the distance between the base and bottom of the battery element.

Abstract: A battery and straps for a battery are disclosed. The battery according to various embodiments comprises a number of straps which connect a number of battery cells in series. The battery straps may pass through cutouts provided in a cell divider wall. The cutouts and straps may define a common headspace. The battery may have five connecting straps and two end straps.

Abstract: Disclosed is a battery comprising a cover; a housing having a base, two side walls, and two end walls; a cell wall spanning between the first and second side walls defining two cells; a battery element provided within a cell, the battery element having a bottom; an element bottom gap, the element bottom gap defined in a first and second dimension by the cell width and length, and a third dimension by the distance between the base and bottom of the battery element.

Abstract: A battery and straps for a battery are disclosed. The battery according to various embodiments comprises a number of straps which connect a number of battery cells in series. The battery straps may pass through cutouts provided in a cell divider wall. The cutouts and straps may define a common headspace. The battery may have five connecting straps and two end straps.

Abstract: A grid for an absorbent glass mat lead acid battery is also disclosed. The grid has a frame formed of a top frame element having a current collection lug, a first side frame element, a second side frame element, and a bottom frame element. A plurality of grid wires are arranged in radial configuration within the frame which radial configuration emanates from a radiant point located outside a boundary of the frame. A plurality of horizontal grid wires cross the plurality of grid wires arranged the radial configuration. The grid comprises virgin lead or high purity lead or highly purified secondary lead. An absorbent glass mat lead acid battery is also disclosed.

Abstract: Disclosed is a battery comprising a cover; a housing having a base, two side walls, and two end walls; a cell wall spanning between the first and second side walls defining two cells; a battery element provided within a cell, the battery element having a bottom; an element bottom gap, the element bottom gap defined in a first and second dimension by the cell width and length, and a third dimension by the distance between the base and bottom of the battery element.

Abstract: A low drop-out regulator circuit comprises a pass transistor providing an output voltage on an output terminal in response to a gate voltage on a gate of the pass transistor. A feedback circuit is coupled to the output terminal to generate a feedback voltage, and an error amplifier provides a drive signal in response to a reference voltage and the feedback voltage. A first gate driver circuit is operable over a first voltage range to provide the gate voltage to the pass transistor in response to the drive signal. A second gate driver circuit is operable over a second voltage range to provide the gate voltage to the pass transistor in response to the drive signal, where the second voltage range is lower than the first voltage range.

Abstract: Techniques for generating a control voltage for a pass transistor of a linear regulator to avoid in-rush current during a start-up phase. In an aspect, a digital comparator is provided to generate a digital output voltage comparing a function of the regulated output voltage with a reference voltage, e.g., a ramp voltage. The digital output voltage is provided to control a plurality of switches selectively coupling the gate of the pass transistor to one of a plurality of discrete voltage levels, e.g., a bias voltage or a ground voltage to turn the pass transistor on or off. In another aspect, the digital techniques may be selectively enabled during a start-up phase of the regulator, and disabled during a normal operation phase of the regulator.

Abstract: In one embodiment, the present disclosure includes a low drop-out regulator circuit comprising a pass transistor providing an output voltage on an output terminal in response to a gate voltage on a gate of the pass transistor. A feedback circuit is coupled to the output terminal to generate a feedback voltage, and an error amplifier provides a drive signal in response to a reference voltage and the feedback voltage. A first gate driver circuit is operable over a first voltage range to provide the gate voltage to the pass transistor in response to the drive signal. A second gate driver circuit is operable over a second voltage range to provide the gate voltage to the pass transistor in response to the drive signal, where the second voltage range is lower than the first voltage range.

Abstract: In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal.

Abstract: In one embodiment, a circuit includes a first transistor having a control terminal, a first terminal, and a second terminal where the first transistor is a first device type. The control terminal of the first transistor receives an input signal. The circuit also includes a second transistor having a control terminal, a first terminal, and a second terminal where the second transistor is a second device type. The control terminal of the second transistor is coupled to the second terminal of the first transistor. A voltage shift circuit has an input coupled to the first terminal of the first transistor and an output coupled to the first terminal of the second transistor and a voltage between the input of the voltage shift circuit and an output of the voltage shift circuit increases as a current from the output of the voltage shift circuit increases.

Abstract: In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal.

Abstract: In one embodiment, a circuit includes a first transistor having a control terminal, a first terminal, and a second terminal where the first transistor is a first device type. The control terminal of the first transistor receives an input signal. The circuit also includes a second transistor having a control terminal, a first terminal, and a second terminal where the second transistor is a second device type. The control terminal of the second transistor is coupled to the second terminal of the first transistor. A voltage shift circuit has an input coupled to the first terminal of the first transistor and an output coupled to the first terminal of the second transistor and a voltage between the input of the voltage shift circuit and an output of the voltage shift circuit increases as a current from the output of the voltage shift circuit increases.

Abstract: Techniques for generating a control voltage for a pass transistor of a linear regulator to avoid in-rush current during a start-up phase. In an aspect, a digital comparator is provided to generate a digital output voltage comparing a function of the regulated output voltage with a reference voltage, e.g., a ramp voltage. The digital output voltage is provided to control a plurality of switches selectively coupling the gate of the pass transistor to one of a plurality of discrete voltage levels, e.g., a bias voltage or a ground voltage to turn the pass transistor on or off. In another aspect, the digital techniques may be selectively enabled during a start-up phase of the regulator, and disabled during a normal operation phase of the regulator.

Abstract: An integrated circuit capacitor structure includes a first wall that serves as a first terminal for each capacitor of a plurality of capacitors. The capacitor structure also includes a plurality of second walls, with each second wall serving as a second terminal for a different capacitor of the plurality of capacitors. The first wall and the second walls stand parallel to each other. In embodiments, the capacitor structure includes a substrate on which the first and the second walls stand perpendicularly. In embodiments, the first wall includes a plurality of first finger regions extending from a first common region of the first wall, and one or more of the first finger regions is at least partially positioned between different second walls.

Abstract: A programmable capacitor bank includes multiple tuning elements. Each tuning element includes two tuning capacitors and a pass transistor that electrically connects or disconnects the capacitors to/from common nodes. For a thermometer decoded capacitor bank, the tuning capacitors for all tuning elements have equal capacitance. Each tuning element further includes at least one pull-up transistor that provides high bias voltage for the pass transistor and at least one pull-down transistor that provides low bias voltage for the pass transistor. The multiple tuning elements may be arranged in a ladder topology such that (1) the tuning elements are turned on in sequential order starting from one end of the ladder and going toward the other end of the ladder and (2) each tuning element receives biasing from a preceding tuning element and provides biasing to a succeeding tuning element. The capacitor bank may be used for VCOs and other circuits.

Abstract: An improved system and method for providing sterile connections. To this end, a device is provided comprising a body, a chamber defined, at least in part, by a portion of the body, the chamber including an interior having a solid sterilizing agent that can sublimate at ambient conditions, and a member that defines., in part, the chamber and is so constructed and arranged to allow the solid sterilizing agent to release in a rate controlled manner through the member.