Abstract: A semiconductor die includes an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section is connected to the first section. The second section is inclined with respect to a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

Abstract: A package includes a photonic integrated circuit die and an electric integrated circuit die. The photonic integrated circuit die includes a substrate and a waveguide. The substrate has a notch and the notch is occupied by air. The waveguide is disposed over the substrate. In a top view, a first portion of the waveguide is overlapped with the substrate and a second portion of the waveguide is overlapped with the notch. The electric integrated circuit die is disposed over the photonic integrated circuit die.

Abstract: A package has a first region and a second region encircled by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die is located in both the first region and the second region. The second die is bonded to the first die and is completely located within the first region. The encapsulant laterally encapsulates the second die. The encapsulant is located in both the first region and the second region. The inductor is completely located within the second region. A metal density in the first region is greater than a metal density in the second region.

Abstract: A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

Abstract: A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die.

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Abstract: A semiconductor package includes a first die and a through via. The through via is electrically connected to the first die. The through via includes a first conductive layer having a first width, a second conductive layer having a second width different from the first width and a first seed layer disposed aside an interface between the first conductive layer and the second conductive layer.

Abstract: A power module is disclosed. The power module includes a first conductive plate, a first power component, and a second power component. The first conductive plate has a first side and a second side opposite to the first side; The first power component is disposed at the first side. The second power component is disposed at a first location of the second side distinct from a second location of the second side. The second location is configured to transfer most heat from the first power component to the second power component if the second power component is disposed at the second location.

Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Abstract: A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.

Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

Abstract: A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of the photonic die. In a top-down view, a boundary of the electronic die is within a boundary of the insulating layer, and the boundary of the insulating layer is within a boundary of the photonic die.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first coil and a second coil of an inductor. The first coil and the second coil are located at different level heights. The first coil includes a first metallic material. The second coil includes a second metallic material. The first metallic material has a different composition from the second metallic material. The second die is bonded to the first die. The second die includes a third coil of the inductor. The inductor extends from the first die to the second die.

Abstract: A semiconductor package including a first die, a second die and a transparent encapsulation material is provided. The first die includes a first substrate and an optical coupler formed on the first substrate. The second die is disposed on the first die and includes a transparent portion overlapping the optical coupler. The transparent encapsulation material is disposed on the first die and laterally encapsulates the second die.

Abstract: The present invention relates to a copolyester that includes following structural units: a first chain segment shown in Formula (I): and a second chain segment shown in Formula (II): where the glass transition temperature (Tg) of the copolyester is 60° C. to 83° C. The present invention also provides a polyester fiber or packaging material containing the copolyester.