Abstract: An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.

Abstract: A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function.

Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.

Abstract: A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.

Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.

Abstract: A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.

Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.

Abstract: A cleaning system for a water-cooled heat exchanger has a collector, a driving device, a condenser, a ball trap and multiple cleaning balls. The collector has an opening, a filtering net, three inlet holes and two outlet holes. The driving device is connected to the collector and has an outlet tube, an inlet tube and a pump. The condenser is connected to the collector and has an inlet, an outlet, multiple copper pipes, an inlet pipe and an overflow pipe. The ball trap is connected to the condenser and the collector and has an inlet end, an outlet end, an internal surface, multiple turbulent blades, an entering pipe and a discharge pipe. The cleaning balls are movably mounted in the collector, the condenser and the ball trap with the cooling water and each cleaning ball has multiple cleaning protrusions and an eccentric rib.

Abstract: The present invention relates to a sheet laminating apparatus for laminating plural sheet articles. The transmitting speed of the sheet laminating apparatus is determined according to the thickness of the sheet articles. By adjusting the transmitting speed, the possibility of getting jammed is minimized. A laminating time upper limit is determined according to the thickness of said sheet articles according to the transmitting speed. The laminating time upper limit is used as an index of discriminating whether a jam event occurs.

Abstract: A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.

Abstract: A comparable circuit employed for parallel testing DRAM devices is disclosed, wherein the disclosed comparable circuit basically encompasses a three-stage circuit composed of two XNOR gates, a XOR gate, and a tri-state output buffer. The first stage consisting of the XOR gate and a first XNOR gate parallel receive the stored test pattern from the detected memory cell to respectively generate a pair of first comparison results. A second exclusive XNOR gate included in the second stage receives the first comparison results, and connects with the third stage through an output terminal of the second XNOR gate. The third stage composed of the output buffer couples with the output terminal of the second XNOR gate to generate a second comparison result further routed to I/O bus. Chess-like test patterns can be employed in the disclosed comparable circuit due to two mutually exclusive logic gates are generated in the first stage.

Abstract: A computer wrist pad having a bottom seat, an outer layer, two end plates, and at least one air sac. The bottom seat is provided with an open-ended receiving space in which the air sac is disposed. The receiving space is sealed off at both ends thereof by the two end plates. The air sac is inflatable and deflatable for adjusting the hardness and the thickness of the computer wrist pad.