Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A method of searching for read voltages includes: respectively reading a memory segment through read voltages to obtain a sampling data, wherein the read voltages are composed of pairs of adjacent read voltages, and the memory segment is from a non-volatile flash memory; counting the number of first bits in each sampling data, wherein the numbers of first bits correspond to the read voltages respectively; obtaining number differences of the first bits corresponding to the pairs of adjacent read voltages; calculating a coefficient matrix according to the read voltages and the differences of the number of first bits; calculating fitting values according to the read voltages and the coefficient matrix, wherein the fitting value corresponds to the read voltage respectively; and selecting a read voltage corresponding to a minimum value among the fitting values to read the memory segment to perform an error correction program.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A method of searching for read voltages includes: respectively reading a memory segment through read voltages to obtain a sampling data, wherein the read voltages are composed of pairs of adjacent read voltages, and the memory segment is from a non-volatile flash memory; counting the number of first bits in each sampling data, wherein the numbers of first bits correspond to the read voltages respectively; obtaining number differences of the first bits corresponding to the pairs of adjacent read voltages; calculating a coefficient matrix according to the read voltages and the differences of the number of first bits; calculating fitting values according to the read voltages and the coefficient matrix, wherein the fitting value corresponds to the read voltage respectively; and selecting a read voltage corresponding to a minimum value among the fitting values to read the memory segment to perform an error correction program.