Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition-subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused multiple multiplication and addition-subtraction indicated by the opcode on four or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused addition and subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused addition and subtraction operation indicated by the opcode on three or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.

Abstract: Apparatus and method for performing vector packed concatenate and shift of portions of quadwords are described herein. An apparatus embodiment includes decoder circuitry to decode a first instruction and execution circuitry to execute the decoded instruction. The execute circuitry includes concatenation circuitry to concatenate a first field from each of a first plurality of data elements with a second field from a corresponding data element of the second plurality of data elements to generate a plurality of concatenated results, and shift circuitry to shift each of the plurality of concatenated results by a number of bit positions specified by a corresponding shift value to generate a plurality of shifted results, wherein a select plurality of bits from each of the plurality of shifted results is stored in a corresponding data element position of a destination register.

Abstract: A processor includes an instruction set architecture that having instructions to perform data parallel multiply on a set of 52-bit integers and further instructions that additionally perform an add or subtract on intermediate products of the data parallel multiply. A 52-bit result of the operations is then zero extended to 64-bits.

Abstract: One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand, a second source operand and a third operand, and second circuitry including a processing resource to execute the decoded instruction. Responsive to the decoded instruction, the processing resource is to output a result of a modular addition operation based on a data element of first source operand data plus a data element of second source operand data modulo a data element of third operand data, provided that the data elements of the first operand data and second operand data are less than the data element of the third operand data.

Abstract: One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.

Abstract: An example private processing pipeline may include: a masked decryption unit to perform a masked decryption operation transforming input data into masked decrypted data; a masked functional unit to produce a masked result by performing a masked operation on the masked decrypted data; and a masked encryption unit to perform a masked encryption operation transforming the masked result into an encrypted result.

Abstract: An example private processing pipeline may include: a masked decryption unit to perform a masked decryption operation transforming input data into masked decrypted data; a masked functional unit to produce a masked result by performing a masked operation on the masked decrypted data; and a masked encryption unit to perform a masked encryption operation transforming the masked result into an encrypted result.

Abstract: Systems, methods, apparatus, and articles of manufacture to prevent unauthorized release of information associated with a function as a service are disclosed. A system disclosed herein operates on in-use information. The system includes a function as a service of a service provider that operates on encrypted data. The encrypted data includes encrypted in-use data. The system also includes a trusted execution environment (TEE) to operate within a cloud-based environment of a cloud provider. The function as a service operates on the encrypted data within the TEE, and the TEE protects service provider information from access by the cloud provider. The encrypted in-use data and the service provider information form at least a portion of the in-use information.