Abstract: A digitally controlled DC-DC converter has a power stage coupled to an input voltage and to a control signal to generate an output voltage in response to the control signal. A controller generates the control signal and has an adjustment block to compare the output voltage to a reference voltage to generate a comparison signal, a logic circuit coupled to the adjustment block to receive the comparison signal and to generate the control signal in response to the comparison signal using a control word, and a digital-to analog converter coupled to the adjustment block, the power stage input voltage and the logic circuit to receive the control word from the logic circuit and to generate a converter voltage representing the control word using another voltage, the converter voltage being applied to the adjustment block to adjust the comparison signal.

Abstract: It is described a voltage regulator device (100), comprising: i) a power device (150), configured to receive an input signal (151) and to produce a corresponding output signal (152); ii) a comparator device (110), coupled via a feedback path (140) to the power device (150), and configured to receive the output signal (152) as a feedback signal (141), and to produce a compared feedback signal (112); and iii) a digital modulation device (120), arranged between the comparator device (110) and the power device (150), and configured to digitally modulate the compared feedback signal (112), and to provide the digitally modulated signal (121) to the power device (150), wherein the digital modulation device (120) comprises: iiia) a delta-sigma (122), iiib) a quantizer (124), and iiic) a feedforward path (128), configured to feedforward the compared feedback signal (112) beyond the delta-sigma (122).

Abstract: There is described a method of controlling a single inductor multiple output, SIMO, switching converter, the method comprising (a) counting, for each output of the multiple outputs of the SIMO switching converter, a period of time during which an output voltage at the respective output is below a corresponding individual threshold value, (b) identifying that output among the multiple outputs of the SIMO switching converter for which the counted period of time is longest, and (c) connecting the identified output to the single inductor of the SIMO switching converter to supply current from the single inductor of the SIMO switching converter to the identified output. Furthermore, a corresponding controller is described.

Abstract: An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

Abstract: A power management circuit includes an electrical power input for receiving electrical power, a controller, a finite state machine circuit in communication with the controller and a first voltage regulator in communication with the controller and the electrical power input and having a first output connected to a first capacitor for storing electrical power and to first electrical circuitry. The controller is configured to cyclically enable the first voltage regulator to supply current to charge the first capacitor. The finite state machine circuit is configured to interact with the controller to control the duration of a first time period of a cycle over which the first voltage regulator supplies current to charge the first capacitor and to control the duration of a second time period of the cycle over which the first voltage regulator does not supply current to charge the first capacitor and during which electrical current is receivable by said first electrical circuitry from said first capacitor.

Abstract: A chip includes a first pin coupled to a signal line and a controller to detect a state of the signal line using the first pin. The controller controls output of first power to the signal line through the first pin based on a first state of the signal line and prevents output of the first power to the signal line through the first pin based on a second state of the signal line. The signal line may be coupled to provide second power from a power source to a data storage device.

Abstract: In accordance with a first aspect of the present disclosure, a power converter is disclosed, comprising: an input configured to receive an input voltage; an output configured to provide an output voltage; a power switching block coupled between the input and the output; a controller configured to control the power switching block, wherein the controller is configured to open and close switches comprised in the power switching block, wherein the controller is further configured to control a resistance of the power switching block. In accordance with a second aspect of the present disclosure, a corresponding method of operating a power converter is conceived.

Abstract: An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

Abstract: A power management circuit includes an electrical power input for receiving electrical power, a controller, a finite state machine circuit in communication with the controller and a first voltage regulator in communication with the controller and the electrical power input and having a first output connected to a first capacitor for storing electrical power and to first electrical circuitry. The controller is configured to cyclically enable the first voltage regulator to supply current to charge the first capacitor. The finite state machine circuit is configured to interact with the controller to control the duration of a first time period of a cycle over which the first voltage regulator supplies current to charge the first capacitor and to control the duration of a second time period of the cycle over which the first voltage regulator does not supply current to charge the first capacitor and during which electrical current is receivable by said first electrical circuitry from said first capacitor.

Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.

Abstract: In accordance with a first aspect of the present disclosure, a power converter is disclosed, comprising: an input configured to receive an input voltage; an output configured to provide an output voltage; a power switching block coupled between the input and the output; a controller configured to control the power switching block, wherein the controller is configured to open and close switches comprised in the power switching block, wherein the controller is further configured to control a resistance of the power switching block. In accordance with a second aspect of the present disclosure, a corresponding method of operating a power converter is conceived.

Abstract: A chip includes a first pin coupled to a signal line and a controller to detect a state of the signal line using the first pin. The controller controls output of first power to the signal line through the first pin based on a first state of the signal line and prevents output of the first power to the signal line through the first pin based on a second state of the signal line. The signal line may be coupled to provide second power from a power source to a data storage device.

Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.

Abstract: This specification discloses methods and systems for reducing negative undershoot during transient load response for a PWM (Pulse Width Modulation) boost power converter. In some embodiments, reduction of negative undershoot during transient load response is achieved by overriding the PWM duty cycle to a maximum duty cycle when VDDBOOST drops during load step. This maximum duty cycle (“max”) mode is triggered when VDDBOOST is within a hysteresis window. Setpoint for maximum duty cycle is versus DCDC converter output and input voltage. In some embodiments, a lookup table is implemented for determining the setpoint for maximum duty cycle.

Abstract: This specification discloses methods and systems for reducing negative undershoot during transient load response for a PWM (Pulse Width Modulation) boost power converter. In some embodiments, reduction of negative undershoot during transient load response is achieved by overriding the PWM duty cycle to a maximum duty cycle when VDDBOOST drops during load step. This maximum duty cycle (“max”) mode is triggered when VDDBOOST is within a hysteresis window. Setpoint for maximum duty cycle is versus DCDC converter output and input voltage. In some embodiments, a lookup table is implemented for determining the setpoint for maximum duty cycle.

Abstract: Various embodiments relate to an apparatus and associated method for a contactless front-end (CLF) managing a secure element (SE). When the SE receives a low power, a monitoring circuit in the CLF may monitor a power supplied to the SE. Upon detection of an under-voltage condition, the monitoring circuit may cause a management module in the CLF to react to the detected under-voltage condition with an SE management technique. The management module may enact the SE management technique through a separate communications interface connected to the SE. In some embodiments, the CLF may further comprise a register that maintains an under-voltage flag that is triggered when the monitoring circuit detects an under-voltage condition. The management module may reset the under-voltage flag and may use the triggering of the under-voltage flag one or more times to determine whether to react through use of a SE management technique.

Abstract: Various embodiments relate to an apparatus and associated method for a contactless front-end (CLF) managing a secure element (SE). When the SE receives a low power, a monitoring circuit in the CLF may monitor a power supplied to the SE. Upon detection of an under-voltage condition, the monitoring circuit may cause a management module in the CLF to react to the detected under-voltage condition with an SE management technique. The management module may enact the SE management technique through a separate communications interface connected to the SE. In some embodiments, the CLF may further comprise a register that maintains an under-voltage flag that is triggered when the monitoring circuit detects an under-voltage condition. The management module may reset the under-voltage flag and may use the triggering of the under-voltage flag one or more times to determine whether to react through use of a SE management technique.

Abstract: A signal transformation arrangement comprises a first input tap (1) to receive a first input signal (IN_P), a first output terminal (3) to provide a first output signal (OUT_P) and a first coupling circuit (10) which couples the first input tap (1) to a first energy storing device (11) depending on a first clock signal (CLK—1) and which couples the first energy storing device (11) to the first output terminal (3) depending on a first inverted clock signal (XCLK—1). The signal transformation arrangement further comprises a second coupling circuit (20) which couples the first input tap (1) to a second energy storing device (21) depending on a second clock signal (CLK—2) and which couples the second energy storing device (21) to the first output terminal (3) depending on a second inverted clock signal (XCLK—2).

Abstract: A signal transformation arrangement comprises a first input tap (1) to receive a first input signal (IN_P), a first output terminal (3) to provide a first output signal (OUT_P) and a first coupling circuit (10) which couples the first input tap (1) to a first energy storing device (11) depending on a first clock signal (CLK—1) and which couples the first energy storing device (11) to the first output terminal (3) depending on a first inverted clock signal (XCLK—1). The signal transformation arrangement further comprises a second coupling circuit (20) which couples the first input tap (1) to a second energy storing device (21) depending on a second clock signal (CLK—2) and which couples the second energy storing device (21) to the first output terminal (3) depending on a second inverted clock signal (XCLK—2).