Abstract: The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be processed and the component may process several applications at the same time. The choice of the grain, control at several levels with limited control interconnection resources and the data distribution circuit enable local or general reconfiguration of the component in one clock cycle.

Abstract: This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous “send/accept” type protocol. The invention also relates to a network on chip used to implement this method.

Abstract: The invention relates to a data processing method in a network on chip formed of a plurality of resources (310,320) capable of communicating with one another and of processing and at least one network controller (300) capable of initialising the communications in the network by initialisation of a credit system, the process comprising at least one communication step between at least one first resource (310) and at least one second resource (320), said communication step comprising: at least one emission by the first resource of a first plurality of special data or “credits” destined for the second resource, at least one receipt by the first resource of a first plurality of data to process sent by the second resource, the emission by the second data resource destined for first resource being authorised following the receipt by the second resource of credits emitted by the first resource.

Abstract: This invention relates to a method for reconfiguring a network of parallel functional elements tolerant to the faults of these functional elements including said basic functional elements (P), spare functional elements (Sp), interconnecting elements (Cm) of these functional elements and a control unit, said method comprising: a step of positioning the functional elements of the logic network on the physical network; a routing step of programming interconnecting elements on the physical network, by choosing a maximum number of interconnecting elements which can be passed between two neighbouring processors using a shortest track search algorithm.

Abstract: This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.