Patents by Inventor Fabio Alessio Marino

Fabio Alessio Marino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210016526
    Abstract: A new system a comprising a balanced belt that forms a ring around a wheel rim and enables smart wheel functionalities as positioning, sensing, actuation and communication hub is presented. The belt can be implemented as a removable apparatus locked around the wheel rim or as an integrate apparatus embedded in the wheel rim by a proper wheel rim manufacturing modification. The belt contains a tank filled with a sealing foam, which, in the event of a punctured tire, can be expelled out of the tank and injected into the inner part of the tire to repair the hole. With respect to the state-of-the-art systems, the proposed self-repairing tire solution, allows to avoid the cumbersome manual tire repairing operations, to save driver stress and time and to enhance car safety. Moreover, the proposed apparatus, by preserving punctured tire damaging, is very cost-effective respect to competitor solutions and contributes to carbon dioxide emission reduction.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Applicant: Repairing Inc.
    Inventor: Fabio Alessio Marino
  • Patent number: 10840387
    Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: November 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Fabio Alessio Marino, Sinan Goktepeli, Narasimhulu Kanike, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
  • Patent number: 10622492
    Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, an insulative layer, and a first non-insulative region, the insulative layer being disposed between the semiconductor region and the first non-insulative region. In certain aspects, the semiconductor variable capacitor may also include a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, the second non-insulative region and the third non-insulative region having different doping types. In certain aspects, the semiconductor variable capacitor may also include an implant region disposed between the semiconductor region and the insulative layer. The implant region may be used to adjust the flat-band voltage of the semiconductor variable capacitor.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Fabio Alessio Marino, Narasimhulu Kanike, Francesco Carobolante, Paolo Menegoli, Qingqing Liang
  • Patent number: 10608124
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Fabio Alessio Marino, Narasimhulu Kanike, Plamen Vassilev Kolev, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
  • Publication number: 20190380682
    Abstract: The present invention describes a method to shape and control acoustic and pressure waves through to the use of metasurfaces applied to the waves. In particular the present invention describes a method to make the use of metasurfaces, for long wavelength waves, like the sound and haptic waves, convenient and practical by up-converting to higher frequency the original signal. Ultrasonic waves reduce the size of the metastructures within the metasurfaces to become small enough to open new frontier in the control of acoustic and pressure waves. The metasurfaces can be made tunable to widen even more the possible applications for metasurface technologies.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 19, 2019
    Inventors: Paolo Menegoli, Fabio Alessio Marino
  • Publication number: 20190326448
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Inventors: Sinan GOKTEPELI, Fabio Alessio MARINO, Narasimhulu KANIKE, Plamen Vassilev KOLEV, Qingqing LIANG, Paolo MENEGOLI, Francesco CAROBOLANTE, Aristotele HADJICHRISTOS
  • Publication number: 20190312152
    Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 10, 2019
    Inventors: Fabio Alessio MARINO, Sinan GOKTEPELI, Narasimhulu KANIKE, Qingqing LIANG, Paolo MENEGOLI, Francesco CAROBOLANTE, Aristotele HADJICHRISTOS
  • Publication number: 20190305143
    Abstract: In certain aspects, a variable capacitor comprises a well having a first side and a second side, an N+ diffusion abutted the well at the first side, a P+ diffusion abutted the well at the second side, and an insulator on the well. The variable capacitor further comprises a gate plate on the insulator having a first gate segment and a second gate segment, wherein the first gate segment and the second gate segment are configured to have different work functions.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Fabio Alessio MARINO, Narasimhulu KANIKE, Qingqing LIANG, Francesco CAROBOLANTE, Paolo MENEGOLI
  • Publication number: 20190295125
    Abstract: The present invention describes an autonomous building system capable of operating based on processing and analysis of collected data by means of Artificial Intelligence algorithms. The data can be gathered from within the system and/or from external networks. The autonomous building system will assist its users in every tasks from enhanced security to energy savings, from health monitoring and data collection to education, from financial assistance to social activities. In particular the described autonomous building is capable of making autonomous decisions and online purchases getting funds out of a dedicated financial account. The autonomous building may become the target of contextual advertising to promote products and/or services.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Applicant: Awenyx Inc.
    Inventors: Fabio Alessio Marino, Paolo Menegoli
  • Patent number: 10424641
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a first semiconductor region; a first non-insulative region disposed adjacent to a first lateral side of the first semiconductor region; a second non-insulative region disposed adjacent to a second lateral side of the first semiconductor region, the second lateral side being opposite to the first lateral side; a second semiconductor region disposed adjacent to a third lateral side of the first semiconductor region, the second semiconductor region and the first semiconductor region having at least one of different doping types or different doping concentrations; an insulative layer adjacent to a top side of the first semiconductor region; and a third non-insulative region, the insulative layer being disposed between the third non-insulative region and the first semiconductor region.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Francesco Carobolante, Fabio Alessio Marino, Narasimhulu Kanike, Paolo Menegoli, Aristotele Hadjichristos
  • Patent number: 10418465
    Abstract: Certain aspects of the present disclosure provide a memory device. One example memory device generally includes a first semiconductor region having a first region, a second region, and a third region, the second region being between the first region and the third region and having a different doping type than the first region and the third region. In certain aspects, the memory device also includes a first non-insulative region, a first insulative region being disposed between the first non-insulative region and the first semiconductor region. In certain aspects, the memory device may include a second non-insulative region, and a second insulative region disposed between the second region and the second non-insulative region, wherein the first insulative region and the second insulative region are disposed adjacent to opposite sides of the second region.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Francesco Carobolante, Sinan Goktepeli, George Imthurn, Fabio Alessio Marino, Narasimhulu Kanike
  • Publication number: 20190280125
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Inventors: Narasimhulu KANIKE, Qingqing LIANG, Fabio Alessio MARINO, Francesco CAROBOLANTE
  • Publication number: 20190221677
    Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, an insulative layer, and a first non-insulative region, the insulative layer being disposed between the semiconductor region and the first non-insulative region. In certain aspects, the semiconductor variable capacitor may also include a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, the second non-insulative region and the third non-insulative region having different doping types. In certain aspects, the semiconductor variable capacitor may also include an implant region disposed between the semiconductor region and the insulative layer. The implant region may be used to adjust the flat-band voltage of the semiconductor variable capacitor.
    Type: Application
    Filed: January 15, 2018
    Publication date: July 18, 2019
    Inventors: Fabio Alessio MARINO, Narasimhulu KANIKE, Francesco CAROBOLANTE, Paolo MENEGOLI, Qingqing LIANG
  • Patent number: 10355134
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Narasimhulu Kanike, Qingqing Liang, Fabio Alessio Marino, Francesco Carobolante
  • Patent number: 10340395
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Fabio Alessio Marino, Qingqing Liang, Francesco Carobolante, Seung Hyuk Kang
  • Patent number: 10319866
    Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a semiconductor region, an insulative layer disposed above the semiconductor region, and a first non-insulative region disposed above the insulative layer. In certain aspects, a second non-insulative region is disposed adjacent to the semiconductor region, and a control region is disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Fabio Alessio Marino, Paolo Menegoli, Narasimhulu Kanike, Francesco Carobolante
  • Patent number: 10211347
    Abstract: Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes an insulative layer, and a semiconductor region disposed adjacent to a first side of the insulative layer. The semiconductor capacitor also includes a first non-insulative region disposed adjacent to a second side of the insulative layer. In certain aspects, the semiconductor region may include a second non-insulative region, wherein the semiconductor region includes at least two regions having at least one of different doping concentrations or different doping types, and wherein one or more junctions between the at least two regions are disposed above or below the first non-insulative region.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Fabio Alessio Marino, Narasimhulu Kanike, Qingqing Liang, Francesco Carobolante, Paolo Menegoli
  • Patent number: 10181533
    Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Fabio Alessio Marino, Paolo Menegoli, Narasimhulu Kanike, Francesco Carobolante, Qingqing Liang
  • Publication number: 20190006530
    Abstract: Certain aspects of the present disclosure provide a variable capacitor. The variable capacitor generally includes a semiconductor region, a dielectric layer disposed adjacent to the semiconductor region, and a first non-insulative region disposed above the dielectric layer, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, a doping concentration of the semiconductor region changes as a function of a distance across the semiconductor region from the dielectric layer or the second non-insulative region.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Fabio Alessio MARINO, Paolo MENEGOLI, Narasimhulu KANIKE, Qingqing LIANG, Francesco CAROBOLANTE
  • Publication number: 20180374963
    Abstract: Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes an insulative layer, and a semiconductor region disposed adjacent to a first side of the insulative layer. The semiconductor capacitor also includes a first non-insulative region disposed adjacent to a second side of the insulative layer. In certain aspects, the semiconductor region may include a second non-insulative region, wherein the semiconductor region includes at least two regions having at least one of different doping concentrations or different doping types, and wherein one or more junctions between the at least two regions are disposed above or below the first non-insulative region.
    Type: Application
    Filed: September 15, 2017
    Publication date: December 27, 2018
    Inventors: Fabio Alessio MARINO, Narasimhulu KANIKE, Qingqing LIANG, Francesco CAROBOLANTE, Paolo MENEGOLI