Patents by Inventor Fabio Giuseppe DE AMBROGGI

Fabio Giuseppe DE AMBROGGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11630671
    Abstract: A device includes a circular buffer, which, in operation, is organized into a plurality of subsets of buffers, and control circuitry coupled to the circular buffer. The control circuitry, in operation, receives a memory load command to load a set of data into the circular buffer. The memory load command has an offset parameter indicating a data offset and a subset parameter indicating a subset of the plurality of subsets into which the circular buffer is organized. The control circuitry responds to the command by identifying a set of buffer addresses of the circular buffer based on a value of the offset parameter and a value of the subset parameter, and loading the set of data into the circular buffer using the identified set of buffer addresses.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 18, 2023
    Assignees: STMICROELECTRONICS (BEIJING) R&D CO., LTD., STMICROELECTRONICS S.r.l.
    Inventors: Xiao Kang Jiao, Fabio Giuseppe De Ambroggi
  • Publication number: 20220414420
    Abstract: Data structure and microcontroller architecture performing binary multiply-accumulate operations using multiple partial copies of weights. Destination-register location, source-register location, and weight-register location are received. Using the weight-register location, a sub-set of the weight bits is copied a select number of times based on a filter index value that is received. Each copy of the sub-set of weights is executed in parallel. Using the source-register location, a sub-set of the input bits is selected based on the size of the sub-set of weights, wherein the sub-set of input bits is shifted one bit from a previous sub-set of input bits. XOR operation is performed on each corresponding bit in the copy of the sub-set of weights with each corresponding bit in the selected sub-set of input bits. In a corresponding destination sub-location, output of each XOR operation is aggregated with each other and with current value of the corresponding destination sub-location.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 29, 2022
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Loris LUISE, Surinder Pal SINGH, Fabio Giuseppe DE AMBROGGI
  • Patent number: 11537840
    Abstract: A neural network classifies an input signal. For example, an accelerometer signal may be classified to detect human activity. In a first convolutional layer, two-valued weights are applied to the input signal. In a first two-valued function layer coupled at input to an output of the first convolutional layer, a two-valued function is applied. In a second convolutional layer coupled at input to an output of the first two-valued functional layer, weights of the second convolutional layer are applied. In a fully-connected layer coupled at input to an output of the second convolutional layer, two-valued weights of the fully connected layer are applied. In a second two-valued function layer coupled at input to an output of the fully connected layer, a two-valued function of the second two-valued function layer is applied. A classifier classifies the input signal based on an output signal of second two-valued function layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 27, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Danilo Pietro Pau, Emanuele Plebani, Fabio Giuseppe De Ambroggi, Floriana Guido, Angelo Bosco
  • Publication number: 20210303267
    Abstract: A method includes retrieving a plurality of datasets from respective memory registers of a memory and storing the retrieved plurality of datasets in respective register portions of a first register. A dataset of data-processing coefficients are stored in a second register. First processing is applied using, as the first operand, a first sub-set of dataset elements stored in the first register, and using, as the second operand, the data-processing coefficients, obtaining a first result. Second processing is applied using, as the first operand, a second sub-set of dataset elements stored in the first register comprised in a second window having a size equal to the dataset size, and using, as the second operand, the replica of the dataset of data-processing coefficients, obtaining a second result. An output is generated based on the first and second results. The first and second processing may perform multiply accumulate (MAC) operations.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 30, 2021
    Inventors: Xiao Kang JIAO, Fabio Giuseppe DE AMBROGGI, Loris LUISE
  • Publication number: 20190147338
    Abstract: A neural network classifies an input signal. For example, an accelerometer signal may be classified to detect human activity. In a first convolutional layer, two-valued weights are applied to the input signal. In a first two-valued function layer coupled at input to an output of the first convolutional layer, a two-valued function is applied. In a second convolutional layer coupled at input to an output of the first two-valued functional layer, weights of the second convolutional layer are applied. In a fully-connected layer coupled at input to an output of the second convolutional layer, two-valued weights of the fully connected layer are applied. In a second two-valued function layer coupled at input to an output of the fully connected layer, a two-valued function of the second two-valued function layer is applied. A classifier classifies the input signal based on an output signal of second two-valued function layer.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 16, 2019
    Inventors: Danilo Pietro PAU, Emanuele PLEBANI, Fabio Giuseppe DE AMBROGGI, Floriana GUIDO, Angelo BOSCO
  • Publication number: 20180189229
    Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.
    Type: Application
    Filed: February 2, 2017
    Publication date: July 5, 2018
    Inventors: Giuseppe DESOLI, Thomas BOESCH, Nitin CHAWLA, Surinder Pal SINGH, Elio GUIDETTI, Fabio Giuseppe DE AMBROGGI, Tommaso MAJO, Paolo Sergio ZAMBOTTI