Abstract: An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.

Abstract: An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord.